mt90528ag2 Zarlink Semiconductor, mt90528ag2 Datasheet - Page 16

• Manufacturer Part Number: mt90528ag2
• Description: 28-port Primary Rate Circuit Emulation Aal1 Sar
• Manufacturer: Zarlink Semiconductor

2.7
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2.8
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2.9
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2.10
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2.10.1
2.10.1.1
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Individual, per-port, integrated clock-recovery PLL allows for flexible, independent timing on each TDM port.
Per-port Stratum 4 digital PLL supports several clock recovery modes:
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Support for optional external PLL such as MT9042 or MT9044: primary & secondary network references and
primary & secondary LOS references output to external PLL; TDM_CLOCK input from external PLL
Bus clock I/O for operation in backplane mode: C4M/C2M and F0
Per-port TDM_in to TDM_out low-latency loopback (DSTi input stream to DSTo output stream)
Per-port TDM_in to TDM_out loopback through the Segmentation and Reassembly Circular Buffers in
external memory (SDT mode only)
Flexible, multi-stream, per-channel TDM circular-buffer loopback possible in SDT Backplane mode
Loopback provided from incoming UTOPIA FIFO to outgoing UTOPIA FIFO (with or without filtering by
Match and Match Enable registers)
Master clock (MCLK) rate of 66.0 MHz
2.5 Volt core supply and 3.3 Volt I/O supply (5 V tolerant I/Os)
Power consumption: 1.9 W
IEEE 1149 (JTAG) Boundary-Scan Test Access Port
456-pin Plastic BGA
-40qC to +85qC (industrial temperature range)
Wide variety of interrupt source bits, allowing for easy monitoring of MT90528 operation
Associated enable bits which enable or disable assertion of the service request and, ultimately, the IRQ
interrupt pin
External Memory Read Parity Error Alarm
Clock Management
Testing Modes
Miscellaneous
Synchronous clocking - generates DS1 or E1 clock from network reference (19.44 MHz or 8 kHz)
Adaptive clocking - recovers clock from received-data buffer fill-level
SRTS - recovers clock from received RTS (residual time stamp) nibbles
Line-rate clocking - PLL locks to incoming DS1 or E1 clock and reduces jitter
Free-running clocks - PLL provides free-running high-accuracy clock for start-up or no-signal conditions
(accuracy limited by MCLK accuracy)
Direct control of PLL output frequency - offset from centre frequency can be configured via CPU
Interrupts
Module Level Service Requests
External Memory Interface Module
Zarlink Semiconductor Inc.
MT90528
16
Data Sheet