mt90528ag2 Zarlink Semiconductor, mt90528ag2 Datasheet - Page 157

• Manufacturer Part Number: mt90528ag2
• Description: 28-port Primary Rate Circuit Emulation Aal1 Sar
• Manufacturer: Zarlink Semiconductor

Address: 6202 + p*10 (Hex)
Label: TDM2_Pp (where p represents the port number)
Reset Value: 0000 (Hex)
Address: 6200 + p*10 (Hex)
Label: TDM1_Pp (where p represents the port number)
Reset Value: 0000 (Hex)
LATENCY_LPBK
PORT_CONTROL
TDM_SEGMEN_
TDM_SEGMEN_
TDM_SEGMEN_
TDM_SEGMEN_
TDM_DATA_
TDM_LOW_
BASE_ADD
FORMAT
EXT_ENB
Reserved
INT_ENB
Label
Label
Position
Position
14:13
Bit
15
12:9
Bit
8:0
13
14
15
Table 84 - TDM Control Register 1 (one per port)
Table 85 - TDM Control Register 2 (one per port)
Type
R/W
R/W
Type
R/W
R/W
R/W
R/W
R/O
TDM Data Mode.
“00” = No cells generated from this port.
“01” = UDT mode
“10” = SDT mode.
“11” = SDT mode with N>46. This mode should be used when any VC associated with this
port has more than 46 channels.
Low latency loopback.
‘0’ = Normal operation.
‘1’ = Loopback data from DSTi to DSTo.
Note 1: If this bit is set, data from DSTi is output on DSTo, regardless of the value of the
TDM_REASS_PORT_CONTROL bit in TDM Control Register 3 (i.e., even if the port is
apparently inactive, loopback data will be output on DSTo).
Note 2: To use low-latency loopback, the clock edge used to sample the incoming TDM
data (determined by TDM_CLK_POL in this register) must be opposite to the clock edge
used to drive the outgoing TDM data (determined by TDM_REASS_CLK_POL, set at
6204h).
Note 3: The delay through the device in low latency loopback mode is approximately 2
TDM clock cycles.
Segmentation Circular Buffer Base Address. (Applies only to SDT mode.)
Represents bits<19:11> of the SDT Segmentation Circular Buffer word address in external
memory.
Always reads “0000”.
Segmentation TDM Port Control.
‘0’ = Port is not active (data is not transferred from the TDM module to the rest of the
MT90528).
‘1’ = Port is active.
Segmentation Internal Enable Process.
‘0’ = Process is disabled.
‘1’ = Process that writes data/CAS to the TDM input buffer is enabled.
Segmentation External Enable Process. (Applies only to SDT mode.)
‘0’ = Process is disabled.
‘1’ = Process that transfers data from the input buffer to external memory is enabled.
Zarlink Semiconductor Inc.
MT90528
157
Description
Description
Data Sheet