mt90528ag2 Zarlink Semiconductor, mt90528ag2 Datasheet - Page 101

• Manufacturer Part Number: mt90528ag2
• Description: 28-port Primary Rate Circuit Emulation Aal1 Sar
• Manufacturer: Zarlink Semiconductor

The gapping circuit operates as follows: the line rate clock (STiCLK, C4M/C2M, or PLLCLK) must be equal to a
framed clock rate. For DS1, E1, and backplane modes, this rate must be 2.048 MHz. However, the user must
provide this clock differently, depending on the mode being employed. If the port is operating in independent clock
mode, the 2.048 MHz clock is presented on STiCLK and the user should select the port’s STiCLK as the source for
the RTSSEL mux. When operating in Generic backplane mode, the desired 2.048 MHz clock rate is available at
C4M/C2M. Therefore, the user should select C4M/C2M as the source for the RTSSEL mux. When operating in ST-
BUS backplane mode, the C4M/C2M signal has a clock rate of 4.096 MHz. This clock is too high to be the line rate
clock for the port. Therefore, the user must provide an appropriate 2.048 MHz clock on the STiCLK input for the
port. The user must then select the STiCLK input as the source of the RTSSEL mux. This half-rate STiCLK signal
will not be used elsewhere in the port’s circuitry, because the TDM module will use the C4M/C2M clock if it is
programmed in backplane mode. In any case, the signal which is output from the RTSSEL multiplexer is input to the
circuit at “line rate clock”. “N” in the above figure represents the number of channels in the VC (N < 24 for DS1; N <
30 for E1; N < 32 for ST-BUS). Adding the number of channels to the accumulator at the rate of the line rate clock,
the “carry” of the adder provides the desired clock rate. For example, if using a 2.048 MHz line rate with an 18-
channel VC, we want to achieve the following result: carry = 2.048 MHz * (18/32) = 1.152 MHz. Looking at the
hardware implementation, we would see the following:
synchronized to mclk)
Note1: N < 24 for DS1; N < 30 for E1; N < 32 for ST-BUS
Note2: frame size = 32 for DS1/E1/ST-BUS
line rate clock
(2.048 MHz
Table 20 - Sample Gapping Circuitry Calculation (N = 18)
18
18
18
18
18
18
18
18
18
18
18
18
N
Figure 40 - Gapping Circuitry for SDT Operation
accumulator
accumulator
output
Zarlink Semiconductor Inc.
18
22
26
12
30
16
20
N
+
0
4
8
2
6
MT90528
101
accumulator
input
18
22
26
12
30
16
20
24
4
8
2
6
carry
carry
0
1
0
1
0
1
0
1
1
0
1
0
=
linerate
u
------------------------- -
framesize
Data Sheet
N