mt90528ag2 Zarlink Semiconductor, mt90528ag2 Datasheet - Page 119

• Manufacturer Part Number: mt90528ag2
• Description: 28-port Primary Rate Circuit Emulation Aal1 Sar
• Manufacturer: Zarlink Semiconductor

Clock Management Module
Main Clocking Registers
Per-Port Clocking Registers
Port 0
Port 1
Port 2
Port 3
Port 4
Address
Byte
Hex
426A
426C
426E
4264
4266
4268
5000
5002
5200
5202
5204
5206
5208
5210
5212
5214
5216
5218
5220
5222
5224
5226
5228
5230
5232
5234
5236
5238
5240
5242
5244
5246
5248
Reset
Value
0000
0000
0000
0000
0000
0000
0001
0000
0000
8000
0000
0000
0001
0000
8000
0000
0000
0001
0000
8000
0000
0000
0001
0000
8000
0000
0000
0001
0000
8000
0000
0000
0001
CSFSR_P0
CSFSR_P1
CSFSR_P2
CSFSR_P3
CSFSR_P4
PLLEN_P0
PLLEN_P1
PLLEN_P2
PLLEN_P3
PLLEN_P4
CDDR_P0
CDDR_P1
CDDR_P2
CDDR_P3
CDDR_P4
CPAR_P0
CPAR_P1
CPAR_P2
CPAR_P3
CPAR_P4
UVC_P25
UVP_P25
UVC_P26
UVP_P26
UVC_P27
UVP_P27
CCR_P0
CCR_P1
CCR_P2
CCR_P3
CCR_P4
Label
PLLCS
CMCR
Table 26 - Register Summary
UDT VPI for Port 25
Clocking Configuration Register
Clocking DCO Difference Register
Clocking Configuration Register
Clocking DCO Difference Register
Clocking Configuration Register
Clocking DCO Difference Register
Clocking Configuration Register
Clocking DCO Difference Register
Clocking Configuration Register
Clocking DCO Difference Register
UDT VCI for Port 25
UDT VCI for Port 26
UDT VPI for Port 26
UDT VCI for Port 27
UDT VPI for Port 27
Clock Management Configuration Register
External PLL Clock Source Register
Clocking Phase Accumulator Register
SRTS FIFO Status Register
PLL Enable Register
Clocking Phase Accumulator Register
SRTS FIFO Status Register
PLL Enable Register
Clocking Phase Accumulator Register
SRTS FIFO Status Register
PLL Enable Register
Clocking Phase Accumulator Register
SRTS FIFO Status Register
PLL Enable Register
Clocking Phase Accumulator Register
SRTS FIFO Status Register
PLL Enable Register
Zarlink Semiconductor Inc.
MT90528
119
Description
Data Sheet