mt90528ag2 Zarlink Semiconductor, mt90528ag2 Datasheet - Page 136

• Manufacturer Part Number: mt90528ag2
• Description: 28-port Primary Rate Circuit Emulation Aal1 Sar
• Manufacturer: Zarlink Semiconductor

6.2.4
Address: 2022 (Hex)
Label: DRSR
Reset Value: 0000 (Hex)
Address: 2020 (Hex)
Label: DRCR
Reset Value: 0000 (Hex)
DRCCR_SE
DRBHF_SE
DROR_SE
DRCA_SE
Reserved
Reserved
Reserved
DRENB
DRCCR
DRBHF
Label
DROR
DRCA
Label
Data RX_SAR Module
Position
Position
15:5
Bit
15:5
0
1
2
3
4
Bit
0
1
2
3
4
Type
R/W
R/W
R/W
R/W
R/W
R/O/L
R/O/L
R/O/L
R/O/L
R/O
Type
R/O
R/O
Table 46 - Data RX_SAR Control Register
Table 47 - Data RX_SAR Status Register
Data RX_SAR Enable.
When cleared, the Data RX_SAR Write Pointer (DRWP at 2026h) is reset to 00h and all
received data cells are ignored.
When set, received data cells are processed normally.
Default of ‘0’ means that the Data RX_SAR is usually disabled.
Data RX_SAR Cell Buffer Overrun Service Enable.
When set, a ‘1’ on DROR in Register 2022h will cause the DATA_RXSAR_SRV bit to be
set in the Main Status Register at 0002h.
Data RX_SAR Cell Arrival Service Enable.
When set, a ‘1’ on DRCA in Register 2022h will cause the DATA_RXSAR_SRV bit to be
set in the Main Status Register at 0002h.
Data RX_SAR Buffer Half Full Service Enable.
When set, a ‘1’ on DRBHF in Register 2022h will cause the DATA_RXSAR_SRV bit to be
set in the Main Status Register at 0002h.
Data RX_SAR Cell Counter Rollover Service Enable.
When set, a ‘1’ on DRCCR in Register 2022h will cause the DATA_RXSAR_SRV bit to be
set in the Main Status Register at 0002h.
Always reads “0000_0000_000”.
Always reads ‘0’.
Data RX_SAR Cell Buffer Overrun Error.
If this bit is set, the DRWP (Register 2026h) = DRRP (Register 2028h). This signifies that
either a non-CBR cell has been overwritten or is about to be overwritten. Software must
take appropriate actions to adjust the read pointer so that further overruns do not occur.
Writing a ‘0’ to this bit clears it.
Data RX_SAR Cell Arrival.
This bit is set each time a data cell is written to the Data RX_SAR Cell Buffer. Writing a ‘0’
to this bit clears it.
Data RX_SAR Buffer Half Full
This bit is set when the buffer is determined to be half full by comparing the read and write
pointers. Writing a ‘0’ to this bit clears it.
Data RX_SAR Cell Counter Rollover.
This bit is set when the Data RX_SAR Cell Counter, located in register 202Ah, overflows.
Writing a ‘0’ to this bit clears it.
Always reads “0000_0000_000”.
Zarlink Semiconductor Inc.
MT90528
136
Description
Description
Data Sheet