mt90528ag2 Zarlink Semiconductor, mt90528ag2 Datasheet - Page 67

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mt90528ag2

Manufacturer Part Number
mt90528ag2
Description
28-port Primary Rate Circuit Emulation Aal1 Sar
Manufacturer
Zarlink Semiconductor
Datasheet
A secondary Data RX_SAR transfers non-CBR cells from the UTOPIA interface to external memory, where the cells
may be processed by user software.
4.6.1
4.6.1.1
At a high level of abstraction, Figure 26 shows the functionality implemented within the UDT RX_SAR and SDT
RX_SAR reassembly paths of the MT90528. Within the “ATM Cell Processing” path there are a number of different
steps which must be taken, depending upon the operating mode of the device. The “Clock Recovery Operations”
and “MIB Statistics Gathering” paths may be taken in conjunction with any of the operating modes.
TDM Data Reassembly
(including dummy-cell
Number Processing
Underrun/Overflow
AAL1-byte Error
Fast Sequence
UDT RX_SAR and SDT RX_SAR Modules
Checking
insertion)
Detection
Data Flow and Processing Path Overview
UDT
Figure 26 - High-Level Overview of the Functionality of the RX_SAR Module
ATM Cell Processing
TDM Data Reassembly
(including dummy-cell
Number Processing
Underrun/Overflow
AAL1-byte Error
Fast Sequence
Error Checking
Basic
Pointer Byte
Checking
Detection
insertion)
SDT
Zarlink Semiconductor Inc.
MT90528
RX_SAR Modules
SRTS
67
ery Operations
Clock Recov-
w/ CAS
CAS Data Reas-
sembly and MF
Adaptive
Indication
MIB Statistics
Gathering
Data Sheet

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