mt90528ag2 Zarlink Semiconductor, mt90528ag2 Datasheet - Page 15

• Manufacturer Part Number: mt90528ag2
• Description: 28-port Primary Rate Circuit Emulation Aal1 Sar
• Manufacturer: Zarlink Semiconductor

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2.5
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2.6
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Supports up to 896 bidirectional TDM channels.
UTOPIA Level 2 compliant 16-bit or 8-bit bus, capable of running at up to 52 MHz
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Capable of operating in UTOPIA Level 1 mode (8-bit bus running at up to 25 MHz), for connection to older
devices
Supports up to 896 bidirectional VCCs (Structured Nx64 mode)
VPI/VCI Match and Match Enable filter prevents excessive look-up table accesses to external memory
Cell reception based on look-up table allows flexible VCC assignment for CBR VCCs (allows non-contiguous
VCC assignment)
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Supports AAL1 Segmentation and Reassembly for Structured and Unstructured CES as specified in af-vtoa-
0078.000
Supports non-multiframe or multiframe circuit emulation, using AAL1 structure formats as described in af-
vtoa-0078.000: Nx64 Basic Service (single frame structure), or DS1 or E1 Nx64 Service with CAS
(multiframe structure)
Supports transmission and reception of up to 128 TDM channels per VCC in accordance with af-vtoa-
0089.001 (ATM Trunking using AAL1 for Narrowband Services)
Supports Unstructured CES and Structured CES simultaneously on different ports
Supports 28 bidirectional VCCs, carrying 1.544 Mbps or 2.048 Mbps, in Unstructured CES mode
Supports up to 896 bidirectional VCCs, carrying from 1 to 128 DS0 (64 kbps) TDM channels, in Structured
CES mode (up to 896 DS0 channels total)
UDT reassembly works with 28 per-port timing engines for fast processing and low delay variation in
Unstructured CES mode (1 VCC per port, for 28 UDT VCCs total)
Low latency in Unstructured CES mode provided by on-chip CDV buffering which does not require any
external memory
Internal CDV buffers of 2048 bytes for each UDT port
Maximum UDT CDV buffering of r4.9 ms in DS1 mode and r 3.7 ms in E1 mode
External CDV buffers of 1024 bytes for each SDT port
Maximum SDT CDV buffering of r63.75 ms (dependent on the Reassembly Circular Buffer size and number
of channels per VC)
Non-CBR data cell transmission and reception for software-implemented SAR function (through non-CBR
Data Cell Buffers in external memory)
Gathers statistical information and provides management statistics for network management through
microprocessor interface
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Low latency in segmentation and reassembly directions
UTOPIA Interface
Segmentation and Reassembly Modules
Accepts data rate of up to 622 Mbps
Supports both “master” (ATM-end) and “slave” (PHY-end) operation
Supports multi-PHY (MPHY) mode when operating as a PHY device
Automatically eliminates null cells (i.e., VPI and VCI = 0)
Look-up table supports up to 65536 VCC entries
Per VCC monitoring compliant with ATMF CES specification Version 2.0 MIB
Zarlink Semiconductor Inc.
MT90528
15
Data Sheet