mt90528ag2 Zarlink Semiconductor, mt90528ag2 Datasheet - Page 144

• Manufacturer Part Number: mt90528ag2
• Description: 28-port Primary Rate Circuit Emulation Aal1 Sar
• Manufacturer: Zarlink Semiconductor

Address: 4000 (Hex)
Label: UCR
Reset Value: 0004 (Hex)
CLAV_TRI_OVERRIDE
DATA_TRI_OVERRIDE
Address: 4002 (Hex)
Label: UNCB
Reset Value: 0000 (Hex)
BACK_TO_BACK
GLOBAL_OAM_SEL
LEVEL1_N_LEVEL2
EIGHT_N_SIXTEEN
DEVICE_ADDRESS
_DISABLED
UTO_CLK_SEL
CONFIGURED
PHY_N_ATM
UTO_CLK_
Label
UKSEL
Label
M
N
Position
Bit
3:0
8:4
9
Position
14:10
Table 62 - UTOPIA Number of Concatenated Bits Register
Bit
15
2
3
4
5
6
7
8
9
Type
R/W
R/W
R/W
Table 61 - UTOPIA Configuration Register
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
M least-significant bits of the VPI used for external memory look-ups. The valid range for
this value is 0 to 12.
N least-significant bits of the VCI used for external memory look-ups. The valid range for
this value is 4 to 16.
When asserted this bit will force the RX UTOPIA ATM state machine to pause after each
cell reception by driving the UTO_IN_ENBATM_ CLAVPHY signal to ‘1’
Selects between an external clock (when set) and an internal clock (when cleared). If an
internal clock is selected, UTO_IN_CLK and UTO_OUT_CLK are outputs, and the fre-
quency of the generated clock is equivalent to MCLK/2. If an external clock is selected,
UTO_IN_CLK and UTO_OUT_CLK are inputs.
Global OAM Select.
When this bit is set, received OAM cells are kept for further processing. When this bit is
low, OAM cells are discarded.
8-bit mode/16-bit mode.
Selects between UTOPIA eight-bit (when set) and sixteen-bit (when cleared) operation.
Level1/Level2.
Selects between UTOPIA Level 1 (when set) and UTOPIA Level 2 (when cleared) oper-
ation.
When this bit is set, cells which have unknown routing according to the look-up table are
placed in the Receive Data Cell Buffer; otherwise these cells are discarded.
When set, this bit forces the CLAV signals to always drive a defined value. When this bit
is cleared, the CLAV signals become high impedance following a clock cycle in which the
MT90528 is not polled.
When set, this bit forces UTO_OUT_SOC and UTO_OUT_DATA to always drive defined
values. When this bit is low, the UTO_OUT_SOC and the UTO_OUT_DATA signals
become high impedance, as defined in the ATM Forum UTOPIA Level 2 specification.
PHY/ATM.
When set, the MT90528’s UTOPIA interface will operate in PHY mode; when the bit is
cleared, the MT90528’s UTOPIA interface will operate in ATM mode.
Defines the address of the MT90528 device used to compare to the UTO_IN_ADD and
UTO_OUT_ADD buses when operating in MPHY mode. Note: Only addresses 00h to
1Eh are valid.
The user must set this bit at least one clock cycle after the UTO_CLK_SEL bit has been
programmed. For normal operation of the UTOPIA port, this bit must be set and
must not be cleared.
This bit should be set only once the UTOPIA is fully programmed (including the LUT,
which should be cleared (all the entries set to 0003h) even if not used).
Zarlink Semiconductor Inc.
MT90528
144
Description
Description
Data Sheet