mt90528ag2 Zarlink Semiconductor, mt90528ag2 Datasheet - Page 64

• Manufacturer Part Number: mt90528ag2
• Description: 28-port Primary Rate Circuit Emulation Aal1 Sar
• Manufacturer: Zarlink Semiconductor

4.5.4
The TX_SAR (and specifically the sub-module which shall henceforth be called the Data TX_SAR) is capable of
transmitting non-CBR data cells which are not associated with any TDM port. These cells may be AAL5 signalling
cells, OAM-type data cells, or any other ATM cells which need to be transmitted from a system containing an
MT90528 device.
The Data TX_SAR does not process or manipulate the data cells. Rather, it simply reads cells which have been
written to a multi-cell circular buffer in external memory by a CPU. It then transfers those cells to the UTOPIA
module for transmission onto the UTOPIA bus.
The Data TX_SAR can operate simultaneously with the generation of AAL1 CBR cells by the TX_SAR.
4.5.4.1
The Data TX_SAR within the MT90528 must be enabled, by setting the Data TX_SAR Enable bit in the Data
TX_SAR Control Register at address 103Eh.
The user writes the cells to a buffer located in external memory. The address and size of this buffer are
programmed in the DTCON register, located at address 1038h. The cell structure format is illustrated in Figure 25.
When the Data TX_SAR is enabled, it begins to send cells from the cell buffer beginning with the cell pointed to by
the Data TX_SAR Read Pointer. The Read Pointer is incremented after each cell is sent. Cell transmission halts
when the Read Pointer is equal to the user-defined Data TX_SAR Write Pointer, which indicates the cell structure
number being written to by the CPU. Cell transmission begins again after the Write Pointer is changed to a different
value than the Read Pointer. The cell buffer is circular; the Read Pointer will never point above the top of the buffer.
UTO_OUT_ENBATM_CLAVPHY
UTO_OUT_CLAVATM_ENBPHY
Data TX_SAR Module
UTO_OUT_DATA[15:0]
Mode of Operation
UTO_OUT_SOC
UTO_OUT_CLK
UTO_OUT_PAR
Figure 24 - Overview of CBR Data Segmentation Process (SDT Mode)
External
ZBT
SRAM
MT90528
UTOPIA Module
UTOPIA
FIFO
TX
Zarlink Semiconductor Inc.
MT90528
Circular Buffers (one
64
SDT Segmentation
per TDM channel)
SDT Segmentation
Control Structure
internal memory)
(one per VC in
TX_SAR
Module (one per
TDM Interface
Buffer
TDM
Input
port)
Data Sheet
DSTi
CSTi
STiCLK
STiMF
.