SC9S12XS256J1MAA FREESCALE [Freescale Semiconductor, Inc], SC9S12XS256J1MAA Datasheet - Page 106
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SC9S12XS256J1MAA
Manufacturer Part Number
SC9S12XS256J1MAA
Description
HCS12 Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.SC9S12XS256J1MAA.pdf
(736 pages)
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1
1
Port Integration Module (S12XSPIMV1)
2.3.49
2.3.50
106
Address 0x025F
Address 0x0260
Read: Anytime.
Write: Anytime.
Read: Anytime. The data source depends on the data direction value.
Write: Anytime.
Field
Field
PIFP
Reset
Reset
PTH
7-0
7-0
W
W
R
R
Port P interrupt flag—
The flag bit is set after an active edge was applied to the associated input pin. This can be a rising or a falling edge
based on the state of the polarity select register.
Writing a logic “1” to the corresponding bit field clears the flag.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set)
0 No active edge occured
Port H general purpose input/output data—Data Register, pin interrupt input/output
The associated pin can be used as general purpose I/O. In general purpose output mode the register bit value is
driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
• Pin interrupts can be generated if enabled in input or output mode.
PIFP7
PTH7
Port P Interrupt Flag Register (PIFP)
Port H Data Register (PTH)
0
0
7
7
PIFP6
PTH6
0
0
6
6
Figure 2-47. Port P Interrupt Flag Register (PIFP)
Table 2-46. PIFP Register Field Descriptions
Table 2-47. PTH Register Field Descriptions
Figure 2-48. Port H Data Register (PTH)
S12XS Family Reference Manual, Rev. 1.09
PIFP5
PTH5
0
0
5
5
PIFP4
PTH4
0
0
4
4
Description
Description
PIFP3
PTH3
3
0
3
0
PIFP2
PTH2
0
0
2
2
Freescale Semiconductor
Access: User read/write
Access: User read/write
PIFP1
PTH1
0
0
1
1
PIFP0
PTH0
0
0
0
0
1
1
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