SC9S12XS256J1MAA FREESCALE [Freescale Semiconductor, Inc], SC9S12XS256J1MAA Datasheet - Page 208

• Manufacturer Part Number: SC9S12XS256J1MAA
• Description: HCS12 Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

S12X Debug (S12XDBGV3) Module
Table 6-28
tagged operations since the trigger occurs based on the tagged opcode reaching the execution stage of the
instruction queue. Thus these bits are ignored if tagged triggering is selected.
6.3.2.8.2
Read: Anytime. See
Write: If DBG not armed. See
208
Address: 0x0029
Bit[22:16]
Reset
Field
COMPE
6–0
Field
W
R
0
shows the effect for RWE and RW on the comparison conditions. These bits are not useful for
Comparator Address High Compare Bits — The Comparator address high compare bits control whether the
selected comparator will compare the address bus bits [22:16] to a logic one or logic zero. .
0 Compare corresponding address bit to a logic zero
1 Compare corresponding address bit to a logic one
0
0
7
Debug Comparator Address High Register (DBGXAH)
Determines if comparator is enabled
0 The comparator is not enabled
1 The comparator is enabled for state sequence triggers or tag generation
RWE Bit
Figure 6-15. Debug Comparator Address High Register (DBGXAH)
Table 6-26
0
0
1
1
1
1
= Unimplemented or Reserved
Bit 22
0
6
Table 6-27. DBGXCTL Field Descriptions (continued)
Table 6-28. Read or Write Comparison Logic Table
RW Bit
Table 6-26
for visible register encoding.
x
x
0
0
1
1
Table 6-29. DBGXAH Field Descriptions
S12XS Family Reference Manual, Rev. 1.09
Bit 21
0
5
RW Signal
for visible register encoding.
0
1
0
1
0
1
Bit 20
0
4
Description
Description
Bit 19
RW not used in comparison
RW not used in comparison
0
3
Comment
No match
No match
Write
Read
Bit 18
0
2
Freescale Semiconductor
Bit 17
0
1
Bit 16
0
0