SC9S12XS256J1MAA FREESCALE [Freescale Semiconductor, Inc], SC9S12XS256J1MAA Datasheet - Page 472
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SC9S12XS256J1MAA
Manufacturer Part Number
SC9S12XS256J1MAA
Description
HCS12 Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.SC9S12XS256J1MAA.pdf
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Timer Module (TIM16B8CV2) Block Description
To operate the 16-bit pulse accumulator independently of input capture or output compare 7 and 0
respectively the user must set the corresponding bits IOSx = 1, OMx = 0 and OLx = 0. OC7M7 in the
OC7M register must also be cleared.
16.3.2.9
Read: Anytime
Write: Anytime.
472
Module Base + 0x000A
Module Base + 0x000B
EDGnB
EDGnA
Reset
Reset
Field
7:0
W
W
R
R
EDG7B
EDG3B
Input Capture Edge Control — These eight pairs of control bits configure the input capture edge detector
circuits.
Timer Control Register 3/Timer Control Register 4 (TCTL3 and TCTL4)
0
0
7
7
EDG7A
EDG3A
0
0
6
6
EDGnB
Table 16-11. Edge Detector Circuit Configuration
Figure 16-16. Timer Control Register 3 (TCTL3)
Figure 16-17. Timer Control Register 4 (TCTL4)
0
0
1
1
Table 16-10. TCTL3/TCTL4 Field Descriptions
S12XS Family Reference Manual, Rev. 1.09
EDG6B
EDG2B
EDGnA
0
0
5
5
0
1
0
1
EDG6A
EDG2A
Capture on any edge (rising or falling)
0
0
4
4
Capture on falling edges only
Capture on rising edges only
Description
Capture disabled
Configuration
EDG5B
EDG1B
0
0
3
3
EDG5A
EDG1A
0
0
2
2
EDG4B
EDG0B
Freescale Semiconductor
0
0
1
1
EDG4A
EDG0A
0
0
0
0
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