SC9S12XS256J1MAA FREESCALE [Freescale Semiconductor, Inc], SC9S12XS256J1MAA Datasheet - Page 615

• Manufacturer Part Number: SC9S12XS256J1MAA
• Description: HCS12 Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

20.3.2.1
The FCLKDIV register is used to control timed events in program and erase algorithms.
All bits in the FCLKDIV register are readable, bits 6–0 are write once and bit 7 is not writable.
Freescale Semiconductor
FDIV[6:0]
FDIVLD
Address
Offset Module Base + 0x0000
Reset
& Name
0x0010
0x0011
0x0012
0x0013
FRSV2
FRSV3
FRSV4
Field
FOPT
6–0
7
W
R
FDIVLD
Clock Divider Loaded
0 FCLKDIV register has not been written
1 FCLKDIV register has been written since the last reset
Clock Divider Bits — FDIV[6:0] must be set to effectively divide OSCCLK down to generate an internal Flash
clock, FCLK, with a target frequency of 1 MHz for use by the Flash module to control timed events during program
and erase algorithms.
Please refer to
Flash Clock Divider Register (FCLKDIV)
0
7
W
W
W
W
R
R
R
R
NV7
= Unimplemented or Reserved
7
0
0
0
Section 20.4.1, “Flash Command Operations,”
Figure 20-4. FTMR64K1 Register Summary (continued)
0
6
Figure 20-5. Flash Clock Divider Register (FCLKDIV)
= Unimplemented or Reserved
NV6
Table 20-7
6
0
0
0
Table 20-6. FCLKDIV Field Descriptions
S12XS Family Reference Manual, Rev. 1.09
0
5
shows recommended values for FDIV[6:0] based on OSCCLK frequency.
NV5
5
0
0
0
0
4
NV4
Description
4
0
0
0
FDIV[6:0]
0
3
for more information.
NV3
3
0
0
0
64 KByte Flash Module (S12XFTMR64K1V1)
0
2
NV2
2
0
0
0
NV1
0
1
1
0
0
0
NV0
0
0
0
0
0
0
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