SC9S12XS256J1MAA FREESCALE [Freescale Semiconductor, Inc], SC9S12XS256J1MAA Datasheet - Page 216
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SC9S12XS256J1MAA
Manufacturer Part Number
SC9S12XS256J1MAA
Description
HCS12 Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.SC9S12XS256J1MAA.pdf
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S12X Debug (S12XDBGV3) Module
6.4.3
Trigger modes are used as qualifiers for a state sequencer change of state. The control logic determines the
trigger mode and provides a trigger to the state sequencer. The individual trigger modes are described in
the following sections.
6.4.3.1
If a forced trigger comparator match occurs, the trigger immediately initiates a transition to the next state
sequencer state whereby the corresponding flags in DBGSR are set. The state control register for the
current state determines the next state for each trigger. Forced triggers are generated as soon as the
matching address appears on the address bus, which in the case of opcode fetches occurs several cycles
before the opcode execution. For this reason a forced trigger at an opcode address precedes a tagged trigger
at the same address by several cycles.
6.4.3.2
If a CPU12X taghit occurs, a transition to another state sequencer state is initiated and the corresponding
DBGSR flags are set. For a comparator related taghit to occur, the S12XDBG must first generate tags based
on comparator matches. When the tagged instruction reaches the execution stage of the instruction queue
a taghit is generated by the CPU12X. The state control register for the current state determines the next
state for each trigger.
6.4.3.3
Independent of comparator matches it is possible to initiate a tracing session and/or breakpoint by writing
the TRIG bit in DBGC1 to a logic “1”. If configured for begin or mid aligned tracing, this triggers the state
sequencer into the Final State, if configured for end alignment, setting the TRIG bit disarms the module,
ending the session. If breakpoints are enabled, a forced breakpoint request is issued immediately (end
alignment) or when tracing has completed (begin or mid alignment).
6.4.3.4
In case of simultaneous triggers, the priority is resolved according to
is suppressed. It is thus possible to miss a lower priority trigger if it occurs simultaneously with a trigger
of a higher priority. The trigger priorities described in
matches, the match on the lower channel number (0,1,2,3) has priority. The SC[3:0] encoding ensures that
a match leading to final state has priority over all other matches in each state sequencer state. When
configured for range modes a simultaneous match of comparators A and C generates an active match0
whilst match2 is suppressed.
If a write access to DBGC1 with the ARM bit position set occurs simultaneously to a hardware disarm
from an internal trigger event, then the ARM bit is cleared due to the hardware disarm.
216
Priority
Trigger Modes
Forced Trigger On Comparator Match
Trigger On Comparator Related Taghit
TRIG Immediate Trigger
Trigger Priorities
Source
S12XS Family Reference Manual, Rev. 1.09
Table 6-39. Trigger Priorities
Table 6-39
dictate that in the case of simultaneous
Table
Action
6-39. The lower priority trigger
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