SC9S12XS256J1MAA FREESCALE [Freescale Semiconductor, Inc], SC9S12XS256J1MAA Datasheet - Page 124

• Manufacturer Part Number: SC9S12XS256J1MAA
• Description: HCS12 Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Port Integration Module (S12XSPIMV1)
A valid edge on an input is detected if 4 consecutive samples of a passive level are followed by 4
consecutive samples of an active level directly or indirectly.
The filters are continuously clocked by the bus clock in RUN and WAIT mode. In STOP mode the clock
is generated by an RC-oscillator in the Port Integration Module. To maximize current saving the RC
oscillator runs only if the following condition is true on any pin individually:
Sample count <= 4 and interrupt enabled (PIE=1) and interrupt flag not set (PIF=0).
2.5
2.5.1
It is not recommended to write PORTx/PTx and DDRx in a word access. When changing the register pins
from inputs to outputs, the data may have extra transitions during the write access. Initialize the port data
register before enabling the outputs.
124
Initialization Information
Port Data and Data Direction Register writes
1
These values include the spread of the oscillator frequency over tempera-
Uncertain
ture, voltage and process.
Ignored
Pulse
Valid
S12XS Family Reference Manual, Rev. 1.09
Table 2-72. Pulse Detection Criteria
Figure 2-75. Pulse Illustration
3 < t
t
t
pulse
pulse
pulse
STOP
< 4
≤ 3
≥ 4
t
pulse
bus clocks
bus clocks
bus clocks
Unit
Mode
t
pign
STOP
< t
t
t
pulse
pulse
pulse
1
≤ t
< t
≥ t
pign
pval
pval
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