SC9S12XS256J1MAA FREESCALE [Freescale Semiconductor, Inc], SC9S12XS256J1MAA Datasheet - Page 145

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SC9S12XS256J1MAA

Manufacturer Part Number
SC9S12XS256J1MAA
Description
HCS12 Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
Memory Mapping Control (S12XMMCV4)
3.4.3
Chip Bus Control
The MMC controls the address buses and the data buses that interface the S12X masters (CPU, BDM )
with the rest of the system (master buses). In addition the MMC handles all CPU read data bus swapping
operations. All internal resources are connected to specific target buses (see
Figure
3-20).
BDM
CPU
S12X1
S12X0
MMC
Address Decoder & Priority
DBG
Target Bus Controller
XBUS0
Data FLASH
PGMFLASH
RAM
Peripherals
Figure 3-20. MMC Block Diagram
S12XS Family Reference Manual, Rev. 1.09
Freescale Semiconductor
145

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