SC9S12XS256J1MAA FREESCALE [Freescale Semiconductor, Inc], SC9S12XS256J1MAA Datasheet - Page 432

• Manufacturer Part Number: SC9S12XS256J1MAA
• Description: HCS12 Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Serial Communication Interface (S12SCIV5)
14.5.3.1.6
The RXEDGIF interrupt is set when an active edge (falling if RXPOL = 0, rising if RXPOL = 1) on the
RXD pin is detected. Clear RXEDGIF by writing a “1” to the SCIASR1 SCI alternative status register 1.
14.5.3.1.7
The BERRIF interrupt is set when a mismatch between the transmitted and the received data in a single
wire application like LIN was detected. Clear BERRIF by writing a “1” to the SCIASR1 SCI alternative
status register 1. This flag is also cleared if the bit error detect feature is disabled.
14.5.3.1.8
The BKDIF interrupt is set when a break signal was received. Clear BKDIF by writing a “1” to the
SCIASR1 SCI alternative status register 1. This flag is also cleared if break detect feature is disabled.
14.5.4
The SCI interrupt request can be used to bring the CPU out of wait mode.
14.5.5
An active edge on the receive input can be used to bring the CPU out of stop mode.
432
Recovery from Wait Mode
Recovery from Stop Mode
RXEDGIF Description
BERRIF Description
BKDIF Description
S12XS Family Reference Manual, Rev. 1.09
Freescale Semiconductor