SC9S12XS256J1MAA FREESCALE [Freescale Semiconductor, Inc], SC9S12XS256J1MAA Datasheet - Page 149

• Manufacturer Part Number: SC9S12XS256J1MAA
• Description: HCS12 Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Chapter 4
Interrupt (S12XINTV2)
4.1
The XINT module decodes the priority of all system exception requests and provides the applicable vector
for processing the exception to either the CPU or the XGATE module. The XINT module supports:
Each of the I bit maskable interrupt requests can be assigned to one of seven priority levels supporting a
flexible priority scheme. For interrupt requests that are configured to be handled by the CPU, the priority
scheme can be used to implement nested interrupt capability where interrupts from a lower level are
automatically blocked if a higher level interrupt is being processed. Interrupt requests configured to be
handled by the XGATE module can be nested one level deep.
Freescale Semiconductor
Revision
Number
V02.00
V02.04
V02.05
V02.06
•
•
•
•
•
•
•
I bit and X bit maskable interrupt requests
One non-maskable unimplemented op-code trap
One non-maskable software interrupt (SWI) or background debug mode request
One non-maskable system call interrupt (SYS)
Three non-maskable access violation interrupt
One spurious interrupt vector request
Three system reset vector requests
Introduction
Revision Date
20 Mar 2007
11 Jan 2007
07 Jan 2008
01 Jul 2005
The HPRIO register and functionality of the original S12 interrupt module
is no longer supported, since it is superseded by the 7-level interrupt request
priority scheme.
4.3.2.2/4-155
4.3.2.4/4-156
4.5.3.1/4-164
4.1.2/4-150
4.4.6/4-162
Sections
Affected
S12XS Family Reference Manual, Rev. 1.09
Table 4-1. Revision History
Initial V2 release, added new features:
- XGATE threads can be interrupted.
- SYS instruction vector.
- Access violation interrupt vectors.
- Added Notes for devices without XGATE module.
- Fixed priority definition for software exceptions.
- Added clarification of “Wake-up from STOP or WAIT by XIRQ with X bit set”
feature.
NOTE
Description of Changes
149