SC9S12XS256J1MAA FREESCALE [Freescale Semiconductor, Inc], SC9S12XS256J1MAA Datasheet - Page 405
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SC9S12XS256J1MAA
Manufacturer Part Number
SC9S12XS256J1MAA
Description
HCS12 Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.SC9S12XS256J1MAA.pdf
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14.3.2.5
Read: Anytime, if AMAP = 1
Write: Anytime, if AMAP = 1
Freescale Semiconductor
Module Base + 0x0002
BERRM[1:0]
BKDFE
Reset
Field
2:1
0
W
R
BERRM1
Bit Error Mode — Those two bits determines the functionality of the bit error detect feature. See
Break Detect Feature Enable — BKDFE enables the break detect circuitry.
0 Break detect circuit disabled
1 Break detect circuit enabled
0
0
1
1
SCI Alternative Control Register 2 (SCIACR2)
0
0
7
= Unimplemented or Reserved
BERRM0
Figure 14-8. SCI Alternative Control Register 2 (SCIACR2)
0
1
0
1
0
0
6
Bit error detect circuit is disabled
Receive input sampling occurs during the 9th time tick of a transmitted bit
(refer to
Receive input sampling occurs during the 13th time tick of a transmitted bit
(refer to
Reserved
Table 14-8. SCIACR2 Field Descriptions
S12XS Family Reference Manual, Rev. 1.09
Table 14-9. Bit Error Mode Coding
0
0
5
Figure
Figure
14-19)
14-19)
0
0
4
Description
Function
0
0
3
Serial Communication Interface (S12SCIV5)
BERRM1
0
2
BERRM0
0
1
Table
BKDFE
14-9.
0
0
405
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