C509-L_97 SIEMENS [Siemens Semiconductor Group], C509-L_97 Datasheet - Page 140

• Manufacturer Part Number: C509-L_97
• Description: 8-Bit CMOS Microcontroller
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Summary of the TOC loading capability :
Initializing the Compare Register/Compare Latch Circuit
Normally when the compare function is desired the initialization program would just write to the
compare register (called ’register latch’). The compare latch itself cannot be accessed directly by a
move instruction, it is exclusively loaded by the timer overflow signal.
In some very special cases, however, an initial loading of the compare latch could be desirable. lf
the following sequence is observed during initialization then latches, the register and the compare
latch, can be loaded before the compare mode is enabled.
Action:
Select compare mode 1 (CMSEL.x = 0).
Move the compare value for the first timer
period to the compare register CMx (high
byte first).
Switch on compare mode 0 (CMSEL.x = 1).
Move the compare value for the second
timer period to the compare register.
Enable the compare function
(CMEN.x = 1)
Set up the prescaler for the compare timer.
Set specific compare output to low level
(CLR P4.x)
Start the compare timer with a desired value
(write-to-CTREL)
Semiconductor Group
– The CMx registers are - when assigned to the compare timer - protected from direct loading
– Thus, the CPU has a full timer period to load a new compare value: there is no danger of
– When writing a 16-bit compare value, the high byte should be written first since the write-to-
– lf there was no write access to a CMx low byte then no TOC loading will take place.
– Because of the TOC loading, all compare values written to CMx registers are only activated
by the CPU. A register latch couple provides a defined load time at timer overflow.
overwriting compare values which are still needed in the current timer period.
low-byte instruction enables a 16-bit wide TOC loading at next timer overflow.
in the next timer period.
6-62
Comment:
This is also the default value after reset.
In compare mode 1 latch is loaded directly
after a write-to-CMLx. Thus the value slips
directly into the compare latch.
Now select the right compare mode.
The register latch is loaded. This value is
used after the first timer overflow.
The compare output is switched to low level.
Compare function is initialized.
The output will oscillate.
On-Chip Peripheral Components
1997-10-01
C509-L