C509-L_97 SIEMENS [Siemens Semiconductor Group], C509-L_97 Datasheet - Page 205

• Manufacturer Part Number: C509-L_97
• Description: 8-Bit CMOS Microcontroller
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

The SFR IEN3 includes the enable bits for the compare timer 1 overflow interrupt and the general
capture/compare interrupt of the compare timer 1.
compare match with compare register interrupts, the compare, and the serial interface 1 interrupt.
Special Function Register IEN3 (Address BE H )
Bit
–
ECT1
ECC1
The SFR EICC1 includes the enable bits for the specific capture/compare interrupt of the compare
timer 1.
Special Function Register EICC1 (Mapped Address BF H )
Bit
EICC17 -
EICC10
EICC1 is mapped to the SFR IRCON2. It is selected by a double instruction sequence with PDIR
set.
Semiconductor Group
Bit No.
Bit No.
BE H
BF H
EICC17 EICC16 EICC15 EICC14
Function
Reserved bits for future use.
Compare timer 1 overflow interrupt enable
If ECT1 = 0, the interrupt at compare timer 1 overflow is disabled.
Compare timer 1, general capture/compare interrupt enable
This bit enables the interrupt on an capture/compare event in the capture/compare
registers CC10 - CC17. Additionally, the SFR EICC1 must be programmed to
enable the interrupt request. With ECC1=0, the general capture/compare timer 1
interrupt is disabled.
Function
Compare timer 1, specific capture/compare interrupt enable
This bit enables the interrupt on an capture/compare event in the capture/compare
registers CC10 - CC17. When EICC1x=0, the interrupt request flag ICC1x has no
effect on the interrupt unit. EICC17 refers to CC17 etc.
MSB
MSB
7
7
–
6
6
–
5
5
–
4
4
–
7-9
EICC13 EICC12 EICC11 EICC10
ECT1
3
3
ECC1
2
2
1
1
–
Reset Value : XXXX00XX B
LSB
LSB
Interrupt System
0
–
0
Reset Value : FF H
IEN3
EICC1
1997-10-01
C509-L