C509-L_97 SIEMENS [Siemens Semiconductor Group], C509-L_97 Datasheet - Page 230

• Manufacturer Part Number: C509-L_97
• Description: 8-Bit CMOS Microcontroller
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Table 9-1
Status of External Pins During Idle and Software Power Down Mode
Pins
ALE
PSEN
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 9
The watchdog timer is the only peripheral which is automatically stopped during idle mode. The idle
mode makes it possible to “freeze” the processor’s status for a certain time or until an external event
causes the controller to go back into normal operating mode. Since the watchdog timer is stopped
during idle mode, this useful feature of the C509-L is provided even if the watchdog function is used
simultaneously.
lf the idle mode is to be used the pin PE/SWD must be held low. Entering the idle mode is to be done
by two consecutive instructions immediately following each other. The first instruction has to set the
flag bit IDLE (PCON.0) and must not set bit IDLS (PCON.5), the following instruction has to set the
start bit IDLS (PCON.5) and must not set bit IDLE (PCON.0). The hardware ensures that a
concurrent setting of both bits, IDLE and IDLS will not initiate the idle mode. Bits IDLE and IDLS will
automatically be cleared after having been set. lf one of these register bits is read the value shown
is zero (0). This double-instruction sequence is implemented to minimize the chance of
unintentionally entering the idle mode.
Note that PCON is not a bit-addressable register, so the above mentioned sequence for entering
the idle mode is to be done by byte handling instructions.
The following instruction sequence may serve as an example:
The instruction that sets bit IDLS is the last instruction executed before going into idle mode.
Termination of the Idle Mode
Semiconductor Group
– ORLPCON,#00000001B;Set bit IDLE, bit IDLS must not be set
– The idle mode can be terminated by activation of any enabled interrupt. The CPU operation
– The other possibility of terminating the idle mode is a hardware reset. Since the oscillator is
ORLPCON,#00100000B;Set bit IDLS, bit IDLE must not be set
is resumed, the interrupt will be serviced and the next instruction to be executed after the RETI
instruction will be the one following the instruction that set the bit IDLS.
still running, the hardware reset is held active for only two machine cycles for a complete
reset.
Idle Mode
High
High
Float
Data / alternate outputs
Address
Data / alternate outputs
Data / alternate outputs
Data / alternate outputs
Data / alternate outputs
Data / alternate outputs
9-5
Software Power Down Mode
Low
Low
Float
Data / last output
Data
Data / last output
Data / last output
Data / last output
Data / last output
Data / last output
Power Saving Modes
1997-10-01
C509-L