C509-L_97 SIEMENS [Siemens Semiconductor Group], C509-L_97 Datasheet - Page 204
C509-L_97
Manufacturer Part Number
C509-L_97
Description
8-Bit CMOS Microcontroller
Manufacturer
SIEMENS [Siemens Semiconductor Group]
Datasheet
1.C509-L_97.pdf
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The SFR IEN2 includes the enable bits for the compare match with compare register interrupts, the
compare timer overflow interrupt, and the serial interface 1 interrupt.
Special Function Register IEN2 (Address 9A H )
Bit
–
ECR
ECS
ECT
ECMP
ES1
Semiconductor Group
Bit No.
9A H
Function
Reserved bits for future use.
COMCLR register compare match interrupt enable
If ECR = 0, the COMCLR compare match interrupt is disabled.
COMSET register compare match interrupt enable
If ECS = 0, the COMSET compare match interrupt is disabled.
Enable compare timer interrupt enable
If ECT = 0, the compare timer overflow interrupt is disabled.
CM0-7 register compare match interrupt enable
If ECMP = 0, the CM0-7 compare match interrupt is disabled.
Serial Interface 1 interrupt enable
if ES1 = 0, the serial interrupt 1 is disabled.
MSB
7
–
6
–
ECR
5
ECS
4
7-8
ECT
3
ECMP
2
1
–
Reset Value : XX0000X0 B
Interrupt System
LSB
ES1
0
IEN2
1997-10-01
C509-L
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