C509-L_97 SIEMENS [Siemens Semiconductor Group], C509-L_97 Datasheet - Page 196

• Manufacturer Part Number: C509-L_97
• Description: 8-Bit CMOS Microcontroller
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

6.6.6 A/D Converter Calibration
The C509-L A/D converter includes hidden internal calibration mechanisms which assure a save
functionality of the A/D converter according to the DC characteristics. The A/D converter calibration
is implemented in a way that a user program which executes A/D conversions is not affected by its
operation. Further, the user program has no control on the calibration mechanism. The calibration
itself executes two basic functions :
The A/D converter calibration operates in two phases : calibration after a reset operation and
calibration at each A/D conversion. The calibration phases are controlled by a state machine in the
A/D converter. This state machine executes the calibration phases and stores the calibration results
dynamically in a small calibration RAM
After a reset operation the A/D calibration is automatically started. This reset calibration phase
which takes 3328 f
12 MHz oscillator frequency and with the default after reset prescaler value of 8, a reset calibration
time of approx. 2.2 ms is reached. For achieving a proper reset calibration, the f
must satisfy the condition f
After the reset calibration phase the A/D converter is calibrated according to its DC characteristics.
Nevertheless, during the reset calibration phase single or continuous A/D can be executed. In this
case it must be regarded that the reset calibration is interrupted and continued after the end of the
A/D conversion. Therefore, interrupting the reset calibration phase by A/D conversions extends the
total reset calibration time. If the specified total unadjusted error (TUE) has to be valid for an A/D
conversion, it is recommended to start the first A/D conversions after reset when the reset
calibration phase is finished. Depending on the oscillator frequency used, the reset calibration
phase can be possibly shortened by setting ADCL1 and ADCL0 (prescaler value) to its final value
immediately after reset.
After the reset calibration, a second calibration mechanism is initiated. This calibration is coupled
to each A/D conversion. With this second calibration mechanism alternatively offset and linearity
calibration values, stored in the calibration RAM, are always checked when an A/D conversion is
executed and corrected if required.
Semiconductor Group
– Offset calibration
– Linearity calibration
ADC
clocks, alternating offset and linearity calibration is executed. Therefore, at
ADC max
: compensation of the offset error of the internal comparator
: correction of the binary weighted capacitor network
2 MHz.
6-118
On-Chip Peripheral Components
ADC
prescaler value
1997-10-01
C509-L