C509-L_97 SIEMENS [Siemens Semiconductor Group], C509-L_97 Datasheet - Page 227

• Manufacturer Part Number: C509-L_97
• Description: 8-Bit CMOS Microcontroller
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

9.1
To provide power saving modes together with effective protection against unintentional entering of
these modes, the C509-L has an extra pin disabling the use of the power saving modes. As this pin
will most likely be used only in critical applications it is combined with an automatic start of the
watchdog timer (see the description in section 7.8 “Fail Save Mechanisms”). This pin is called PE/
SWD (power saving enable/start watchdog timer) and its function is as follows:
PE/SWD = 1 (logic high level)
PE/SWD = 0 (logic low level)
When left unconnected, the pin PE/SWD is pulled to high level by a weak internal pullup. This is
done to provide system protection by default.
The logic level applied to pin PE/SWD can be changed during program execution in order to allow
or block the use of the power saving modes without any effect on the on-chip watchdog circuitry;
(the watchdog timer is started only if PE/SWD is on high level at the moment when reset is released;
a change at PE/SWD during program execution has no effect on the watchdog timer; this only
enables or disables the use of the power saving modes.). A change of the pin’s level is detected in
state 3, phase 1. A Schmitt trigger is used at the input to reduce susceptibility to noise.
In addition to the hardware enable/disable of the power saving modes, a double-instruction
sequence which is described in the corresponding sections is necessary to enter power down and
idle mode. The combination of all these safety precautions provide a maximum of system
protection.
Application Example for Switching Pin PE/SWD
For most applications in noisy environments, components external to the chip are used to give
warning of a power failure or a turn off of the power supply. These circuits could be used to control
the PE/SWD pin. The possible steps to go into power down mode could then be as follows:
Semiconductor Group
– Use of the power saving modes is not possible. The instruction sequences used for entering
– lf and only if PE/SWD is held at high level during reset, the watchdog timer is started
– All power saving modes can be activated as described in the following sections
– The watchdog timer has to be started by software if system protection is desired.
– A power-fail signal forces the controller to go into a high priority interrupt routine. This interrupt
– Finally the controller enters power down mode by executing the relevant double-instruction
these modes will not affect the normal operation of the device.
immediately after reset is released.
routine saves the actual program status. At the same time pin PE/SWD is pulled low by the
power-fail signal.
sequence.
Hardware Enable for the Use of the Power Saving Modes
9-2
Power Saving Modes
1997-10-01
C509-L