C509-L_97 SIEMENS [Siemens Semiconductor Group], C509-L_97 Datasheet - Page 207

• Manufacturer Part Number: C509-L_97
• Description: 8-Bit CMOS Microcontroller
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

7.2.3 Interrupt Request Flags
The request flags for the different interrupt sources are located in several special function registers.
This section describes the locations and meanings of these interrupt request flags in detail.
The external interrupts 0 and 1 (P3.2/INT0 and P3.3/INT1) can each be either level-activated or
negative transition-activated, depending on bits IT0 and IT1 in SFR TCON. The flags that actually
generate these interrupts are bits IE0 and lE1 in SFR TCON. When an external interrupt is
generated, the flag that generated this interrupt is cleared by the hardware when the service routine
is vectored to, but only if the interrupt was transition-activated. lf the interrupt was level-activated,
then the requesting external source directly controls the request flag, rather than the on-chip
hardware.
The timer 0 and timer 1 interrupts are generated by TF0 and TF1 in register TCON, which are set
by a rollover in their respective timer/counter registers (exception is timer 0 in mode 3). When a
timer interrupt is generated, the flag that generated it is cleared by the on-chip hardware when the
service routine is vectored to.
Special Function Register TCON (Address 88 H )
Bit
TF1
TF0
IE1
IT1
IE0
IT0
Semiconductor Group
Bit No.
88 H
The shaded bits are not used for interrupt purposes.
Function
Timer 1 overflow flag
Set by hardware on timer/counter 1 overflow. Cleared by hardware when
processor vectors to interrupt routine.
Timer 0 overflow flag
Set by hardware on timer/counter 0 overflow. Cleared by hardware
when processor vectors to interrupt routine.
External interrupt 1 request flag
Set by hardware. Cleared by hardware when processor vectors to interrupt routine
(if IT1 = 1) or by hardware (if IT1 = 0).
External interrupt 1 level/edge trigger control flag
If IT1 = 0, level triggered external interrupt 1 is selected.
If IT1 = 1, negative edge triggered external interrupt 1 is selected.
External interrupt 0 request flag
Set by hardware. Cleared by hardware when processor vectors to interrupt routine
(if IT0 = 1) or by hardware (if IT0 = 0).
External interrupt 0 level/edge trigger control flag
If IT0 = 0, level triggered external interrupt 0 is selected.
If IT0 = 1, negative edge triggered external interrupt 0 is selected.
MSB
TF1
8F
H
TR1
8E
H
TF0
8D
H
TR0
8C
H
7-11
IE1
8B
H
IT1
8A
H
IE0
89
H
LSB
IT0
Interrupt System
88
H
Reset Value : 00 H
TCON
1997-10-01
C509-L