C509-L_97 SIEMENS [Siemens Semiconductor Group], C509-L_97 Datasheet - Page 209

• Manufacturer Part Number: C509-L_97
• Description: 8-Bit CMOS Microcontroller
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

The external interrupt 2 (INT2/CC4) can be either positive or negative transition-activated
depending on bit I2FR in register T2CON. The flag that actually generates this interrupt is bit IEX2
in register IRCON. In addition, this flag will be set if a compare event occurs at the corresponding
output pin P1.4/INT2/CC4, regardless of the compare mode established and the transition at the
respective pin. lf an interrupt 2 is generated, flag IEX2 is cleared by hardware when the service
routine is vectored to.
Like the external interrupt 2, the external interrupt 3 can be either positive or negative transition-
activated, depending on bit I3FR in register T2CON. The flag that actually generates this interrupt
is bit IEX3 in register IRCON0. In addition, this flag will be set if a compare event occurs at pin
P1.0/INT3/CC0, regardless of the compare mode established and the transition at the respective
pin. The flag IEX3 is cleared by hardware when the service routine is vectored to.
The external interrupts 4 (INT4), 5 (INT5), 6 (INT6) are positive transition-activated. The flags that
actually generate these interrupts are bits IEX4, IEX5, and IEX6 in register IRCON0. In addition,
these flags will be set if a compare event occurs at the corresponding output pin P1.1/INT4/CC1,
P1.2/INT5/CC2, and P1.3/INT6/CC3, regardless of the compare mode established and the
transition at the respective pin. When an interrupt is generated, the flag that generated it is cleared
by the on-chip hardware when the service routine is vectored to.
The timer 2 interrupt is generated by the logical OR of bit TF2 in SFR T2CON and bit EXF2 in SFR
IRCON0. Neither of these flags is cleared by hardware when the service routine is vectored to. In
fact, the service routine may have to determine whether it was TF2 or EXF2 that generated the
interrupt, and the bit will have to be cleared by software.
The A/D converter interrupt is generated by IADC in register IRCON0. lt is set some cycles before
the result is available. That is, if an interrupt is generated, in any case the converted result in ADDAT
is valid on the first instruction of the interrupt service routine (with respect to the minimal interrupt
response time). lf continuous conversions are established, IADC is set once during each
conversion. lf an A/D converter interrupt is generated, flag IADC must be cleared by software.
Special Function Register T2CON (Address C8 H )
Bit
I3FR
I2FR
Semiconductor Group
Bit No.
C8 H
The shaded bits are not used for interrupt purposes.
Function
External interrupt 3 rising/falling edge control flag
If I3FR = 0, the external interrupt 3 is activated by a negative transition at INT3.
If I3FR = 1, the external interrupt 3 is activated by a positive transition at INT3.
External interrupt 2 rising/falling edge control flag
If I3FR = 0, the external interrupt 3 is activated by a negative transition at INT2.
If I3FR = 1, the external interrupt 3 is activated by a positive transition at INT2.
T2PS
MSB
CF
H
I3FR
CE
H
I2FR
CD
H
T2R1
CC
H
7-13
T2R0
CB
H
T2CM
CA
H
T2I1
C9
H
LSB
T1I0
Interrupt System
C8
Reset Value : 00 H
H
T2CON
1997-10-01
C509-L