C509-L_97 SIEMENS [Siemens Semiconductor Group], C509-L_97 Datasheet - Page 30
C509-L_97
Manufacturer Part Number
C509-L_97
Description
8-Bit CMOS Microcontroller
Manufacturer
SIEMENS [Siemens Semiconductor Group]
Datasheet
1.C509-L_97.pdf
(290 pages)
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Memory Organization
C509-L
3.4.2 Normal Mode Configuration
The Normal Mode is the standard 8051 compatible operating mode of the C509-L. In this mode 64K
byte external code memory and 61K byte external SRAM as well as 3K byte internal data memory
(XRAM) are provided. If the XRAM is disabled (default after reset), totally 64K byte external data
memory are available. The Boot ROM is disabled. The external program memory is controlled by
the PSEN/RDF signal. Read and write accesses to the external data memory are controlled by the
RD and WR pins of port 3.
The Normal Mode is entered by keeping the pin PRGEN at a logic low during the rising edge of the
external RESET or HWPD signal. The locations of the code- and data-memory in Normal Mode are
shown in figure 3-4.
Figure 3-3
Locations of Code- and Data Memory in Normal Mode
Semiconductor Group
3-5
1997-10-01
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