C509-L_97 SIEMENS [Siemens Semiconductor Group], C509-L_97 Datasheet - Page 202
C509-L_97
Manufacturer Part Number
C509-L_97
Description
8-Bit CMOS Microcontroller
Manufacturer
SIEMENS [Siemens Semiconductor Group]
Datasheet
1.C509-L_97.pdf
(290 pages)
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7.2
7.2.1 Interrupt Enable Registers
Each interrupt vector can be individually enabled or disabled by setting or clearing the
corresponding bit in the interrupt enable registers IEN0, IEN1, IEN2. and IEN3. Register IEN0 also
contains the global disable bit (EAL), which can be cleared to disable all interrupts at once. Some
interrupts sources have further enable bits (e.g. EXEN2). Such interrupt enable bits are controlled
by specific bits in the SFRs of the corresponding peripheral units (described in chapter 6). This
section describes the locations and meanings of these interrupt enable bits in detail.
After reset the enable bits of the interrupt enable registers IEN0 to IEN3 are set to 0. That means
that the corresponding interrupts are disabled.
The SFR IEN0 includes the enable bits for the external interrupts 0 and 1, the timer 0,1, and 2
interrupts, the serial interface 0 interrupt, and the general interrupt enable control bit EAL.
Special Function Register IEN0 (Address A8 H )
Bit
EAL
ET2
ES0
ET1
EX1
ET0
EX0
Semiconductor Group
Bit No.
Interrupt Registers
A8 H
The shaded bit is not used for interrupt control
Function
Enable/disable all interrupts.
If EA=0, no interrupt will be acknowledged.
If EA=1, each interrupt source is individually enabled or disabled by setting or
clearing its enable bit.
Timer 2 interrupt enable.
If ET2 = 0, the timer 2 interrupt is disabled.
Serial channel 0 interrupt enable
If ES0 = 0, the serial channel interrupt 0 is disabled.
Timer 1 overflow interrupt enable.
If ET1 = 0, the timer 1 interrupt is disabled.
External interrupt 1 enable.
If EX1 = 0, the external interrupt 1 is disabled.
Timer 0 overflow interrupt enable.
If ET0 = 0, the timer 0 interrupt is disabled.
External interrupt 0 enable.
If EX0 = 0, the external interrupt 0 is disabled.
MSB
EAL
AF
H
WDT
AE
H
ET2
AD
H
ES0
AC
H
7-6
ET1
AB
H
EX1
AA
H
ET0
A9
H
LSB
EX0
Interrupt System
A8
Reset Value : 00 H
H
IEN0
1997-10-01
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