C509-L_97 SIEMENS [Siemens Semiconductor Group], C509-L_97 Datasheet - Page 70

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C509-L_97

Manufacturer Part Number
C509-L_97
Description
8-Bit CMOS Microcontroller
Manufacturer
SIEMENS [Siemens Semiconductor Group]
Datasheet
Reset / System Clock
C509-L
5
Reset and System Clock Operation
5.1
Reset Function and Circuitries
The hardware reset function incorporated in the C509-L allows for an easy automatic start-up at a
minimum of additional hardware and forces the controller to a predefined default state. The
hardware reset function can also be used during normal operation in order to restart the device. This
is particularly done when the power-down mode is to be terminated.
Additionally to the hardware reset, which is applied externally to the C509-L, there are two internal
reset sources, the watchdog timer and the oscillator watchdog. They are described in detail in
section 8 "Fail-Save Mechanisms". The actual chapter only deals with the external hardware reset.
The reset input is an active low input at pin RESET. An internal Schmitt trigger is used at the input
for noise rejection. Since the reset is synchronized internally, the RESET pin must be held low for
at least two machine cycles (12 oscillator periods) while the oscillator is running. With the oscillator
running the internal reset is executed during the second machine cycle in which RESET is low and
is repeated every cycle until RESET goes high again.
During reset, pins ALE and PSEN are configured as inputs and should not be stimulated externally.
(An external stimulation at these lines during reset activates several test modes which are reserved
for test purposes. This in turn may cause unpredictable output operations at several port pins).
V
A pullup resistor is internally connected to
to allow a power-up reset with an external capacitor
CC
V
V
only. An automatic reset can be obtained when
is applied by connecting the reset pin to
via
CC
SS
V
a capacitor as shown in figure 5-1 a) and c). After
has been turned on, the capacitor must hold
CC
the voltage level at the reset pin for a specified time below the upper threshold of the Schmitt trigger
to effect a complete reset.
Semiconductor Group
5-1
1997-10-01

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