ATMEga64L ATMEL Corporation, ATMEga64L Datasheet - Page 139

• Manufacturer Part Number: ATMEga64L
• Description: 8-bit AVR Microcontroller with 64K Bytes In-System Programmable Flash
• Manufacturer: ATMEL Corporation

Extended Timer/Counter
Interrupt Mask Register –
ETIMSK
2490G–AVR–03/04
(1)
• Bit 2 – TOIE1: Timer/Counter1, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Counter1 Overflow Interrupt is enabled. The corresponding
Interrupt Vector (see “Interrupts” on page 59) is executed when the TOV1 flag, located
in TIFR, is set.
Note:
• Bit 7:6 – Reserved Bits
These bits are reserved for future use. For ensuring compatibility with future devices,
these bits must be set to zero when ETIMSK is written.
• Bit 5 – TICIE3: Timer/Counter3, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Counter3 Input Capture interrupt is enabled. The
corresponding Interrupt Vector (see “Interrupts” on page 59) is executed when the ICF3
flag, located in ETIFR, is set.
• Bit 4 – OCIE3A: Timer/Counter3, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Counter3 Output Compare A Match interrupt is enabled. The
corresponding Interrupt Vector (see “Interrupts” on page 59) is executed when the
OCF3A flag, located in ETIFR, is set.
• Bit 3 – OCIE3B: Timer/Counter3, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Counter3 Output Compare B Match interrupt is enabled. The
corresponding Interrupt Vector (see “Interrupts” on page 59) is executed when the
OCF3B flag, located in ETIFR, is set.
• Bit 2 – TOIE3: Timer/Counter3, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Counter3 Overflow Interrupt is enabled. The corresponding
Interrupt Vector (see “Interrupts” on page 59) is executed when the TOV3 flag, located
in ETIFR, is set.
• Bit 1 – OCIE3C: Timer/Counter3, Output Compare C Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Counter3 Output Compare C Match interrupt is enabled. The
corresponding Interrupt Vector (see “Interrupts” on page 59) is executed when the
OCF3C flag, located in ETIFR, is set.
Bit
Read/Write
Initial Value
1. This register is not available in ATmega103 compatibility mode.
R
7
0
–
R
6
–
0
TICIE3
R/W
5
0
OCIE3A
R/W
4
0
OCIE3B
R/W
3
0
TOIE3
R/W
2
0
ATmega64(L)
OCIE3C
R/W
1
0
OCIE1C
R/W
0
0
ETIMSK
139