ATMEga64L ATMEL Corporation, ATMEga64L Datasheet - Page 70

• Manufacturer Part Number: ATMEga64L
• Description: 8-bit AVR Microcontroller with 64K Bytes In-System Programmable Flash
• Manufacturer: ATMEL Corporation

Special Function IO Register –
SFIOR
70
ATmega64(L)
Table 26. Generic Description of Overriding Signals for Alternate Functions
The following subsections shortly describe the alternate functions for each port, and
relate the overriding signals to the alternate function. Refer to the alternate function
description for further details.
• Bit 2 – PUD: Pull-up disable
When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn
and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01).
See “Configuring the Pin” on page 65 for more details about this feature.
Bit
Read/Write
Initial Value
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
Pull-up Override
Pull-up Override
Data Direction
Digital Input Enable
Digital Input Enable
Analog Input/output
Full Name
Enable
Value
Override Enable
Data Direction
Override Value
Port Value Override
Enable
Port Value Override
Value
Override Enable
Override Value
Digital Input
TSM
R/W
7
0
R
6
–
0
Description
If this signal is set, the pull-up enable is controlled by the
PUOV signal. If this signal is cleared, the pull-up is enabled
when {DDxn, PORTxn, PUD} = 0b010.
If PUOE is set, the pull-up is enabled/disabled when PUOV
is set/cleared, regardless of the setting of the DDxn,
PORTxn, and PUD Register bits.
If this signal is set, the Output Driver Enable is controlled by
the DDOV signal. If this signal is cleared, the Output driver is
enabled by the DDxn Register bit.
If DDOE is set, the Output Driver is enabled/disabled when
DDOV is set/cleared, regardless of the setting of the DDxn
Register bit.
If this signal is set and the Output Driver is enabled, the port
value is controlled by the PVOV signal. If PVOE is cleared,
and the Output Driver is enabled, the port Value is controlled
by the PORTxn Register bit.
If PVOE is set, the port value is set to PVOV, regardless of
the setting of the PORTxn Register bit.
If this bit is set, the Digital Input Enable is controlled by the
DIEOV signal. If this signal is cleared, the Digital Input
Enable is determined by MCU state (Normal mode, sleep
modes).
If DIEOE is set, the Digital Input is enabled/disabled when
DIEOV is set/cleared, regardless of the MCU state (Normal
mode, sleep modes).
This is the Digital Input to alternate functions. In the figure,
the signal is connected to the output of the Schmitt Trigger
but before the synchronizer. Unless the Digital Input is used
as a clock source, the module with the alternate function will
use its own synchronizer.
This is the Analog Input/output to/from alternate functions.
The signal is connected directly to the pad, and can be used
bi-directionally.
R
5
–
0
R
4
–
0
ACME
R/W
3
0
PUD
R/W
2
0
PSR0
R/W
1
0
PSR321
R/W
2490G–AVR–03/04
0
0
SFIOR