ATMEga64L ATMEL Corporation, ATMEga64L Datasheet - Page 286

• Manufacturer Part Number: ATMEga64L
• Description: 8-bit AVR Microcontroller with 64K Bytes In-System Programmable Flash
• Manufacturer: ATMEL Corporation

Reading the Fuse and Lock
Bits from Software
Preventing Flash Corruption
286
ATmega64(L)
It is possible to read both the Fuse and Lock bits from software. To read the Lock bits,
load the Z-pointer with 0x0001 and set the BLBSET and SPMEN bits in SPMCSR.
When an LPM instruction is executed within three CPU cycles after the BLBSET and
SPMEN bits are set in SPMCSR, the value of the Lock bits will be loaded in the destina-
tion register. The BLBSET and SPMEN bits will auto-clear upon completion of reading
the Lock bits or if no LPM instruction is executed within three CPU cycles or no SPM
instruction is executed within four CPU cycles. When BLBSET and SPMEN are cleared,
LPM will work as described in the AVR Instruction Set Reference Manual.
The algorithm for reading the Fuse Low bits is similar to the one described above for
reading the Lock bits. To read the Fuse Low bits, load the Z-pointer with 0x0000 and set
the BLBSET and SPMEN bits in SPMCSR. When an LPM instruction is executed within
three cycles after the BLBSET and SPMEN bits are set in the SPMCSR, the value of the
Fuse Low bits (FLB) will be loaded in the destination register as shown below. Refer to
Table 120 on page 292 for a detailed description and mapping of the Fuse Low bits.
Similarly, when reading the Fuse High bits, load 0x0003 in the Z-pointer. When an LPM
instruction is executed within three cycles after the BLBSET and SPMEN bits are set in
the SPMCSR, the value of the Fuse High bits (FHB) will be loaded in the destination
register as shown below. Refer to Table 119 on page 292 for detailed description and
mapping of the Fuse High bits.
When reading the Extended Fuse bits, load 0x0002 in the Z-pointer. When an LPM
instruction is executed within three cycles after the BLBSET and SPMEN bits are set in
the SPMCSR, the value of the Extended Fuse bits (EFB) will be loaded in the destina-
tion register as shown below. Refer to Table 118 on page 291 for detailed description
and mapping of the Fuse High bits.
Fuse and Lock bits that are programmed will be read as zero. Fuse and Lock bits that
are unprogrammed will be read as one.
During periods of low V
age is too low for the CPU and the Flash to operate properly. These issues are the same
as for board level systems using the Flash, and the same design solutions should be
applied.
A Flash program corruption can be caused by two situations when the voltage is too low.
First, a regular write sequence to the Flash requires a minimum voltage to operate cor-
rectly. Second, the CPU itself can execute instructions incorrectly, if the supply voltage
for executing instructions is too low.
Flash corruption can easily be avoided by following these design recommendations (one
is sufficient):
Bit
Rd
Bit
Rd
Bit
Rd
Bit
Rd
FLB7
FHB7
7
–
7
7
7
–
FLB6
FHB6
CC,
6
6
6
–
6
–
the Flash program can be corrupted because the supply volt-
BLB12
FHB5
FLB5
5
5
5
–
5
BLB11
FHB4
FLB4
4
4
4
4
–
BLB02
FLB3
FHB3
3
3
3
3
–
BLB01
FHB2
FLB2
2
2
2
2
–
FHB1
FLB1
EFB1
LB2
1
1
1
1
FHB0
EFB0
FLB0
LB1
2490G–AVR–03/04
0
0
0
0