ATMEga64L ATMEL Corporation, ATMEga64L Datasheet - Page 351

no-image

ATMEga64L

Manufacturer Part Number
ATMEga64L
Description
8-bit AVR Microcontroller with 64K Bytes In-System Programmable Flash
Manufacturer
ATMEL Corporation
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEga64L-16AU
Manufacturer:
ROHM
Quantity:
40 000
Part Number:
ATMEga64L-8AC
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
ATMEga64L-8AI
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
ATMEga64L-8AI
Manufacturer:
ALTERA
0
Part Number:
ATMEga64L-8AI
Manufacturer:
AT
Quantity:
20 000
Part Number:
ATMEga64L-8AJ
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
ATMEga64L-8AQ
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
ATMEga64L-8AQ
Manufacturer:
AT
Quantity:
20 000
Part Number:
ATMEga64L-8AU
Manufacturer:
ATMEL
Quantity:
4 000
Part Number:
ATMEga64L-8AU
Manufacturer:
ATMEL
Quantity:
451
Part Number:
ATMEga64L-8AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
ATMEga64L-8MI
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
ATMEga64L-8MU
Quantity:
113
Part Number:
ATMEga64L-8MUR
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
ATMEga64L8AJ
Manufacturer:
ATMEL
Quantity:
6 973
Errata
ATmega64, all rev.
2490G–AVR–03/04
The revision letter in this section refers to the revision of the ATmega64 device.
1. Stabilizing time needed when changing XDIV Register
2. Stabilizing time needed when changing OSCCAL Register
A proposal for solving problems regarding the JTAG instruction IDCODE is presented
below.
Stabilizing time needed when changing XDIV Register
Stabilizing time needed when changing OSCCAL Register
After increasing the source clock frequency more than 2% with settings in the XDIV
register, the device may execute some of the subsequent instructions incorrectly.
Problem Fix / Workaround
The NOP instruction will always be executed correctly also right after a frequency
change. Thus, the next 8 instructions after the change should be NOP instructions.
To ensure this, follow this procedure:
1.Clear the I bit in the SREG Register.
2.Set the new pre-scaling factor in XDIV register.
3.Execute 8 NOP instructions
4.Set the I bit in SREG
This will ensure that all subsequent instructions will execute correctly.
Assembly Code Example:
CLI
OUT
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
SEI
After increasing the source clock frequency more than 2% with settings in the OSC-
CAL register, the device may execute some of the subsequent instructions
incorrectly.
Problem Fix / Workaround
The behavior follows errata number 1., and the same Fix / Workaround is applicable
on this errata.
IDCODE masks data from TDI input
The public but optional JTAG instruction IDCODE is not implemented correctly
according to IEEE1149.1; a logic one is scanned into the shift register instead of the
TDI input while shifting the Device ID Register. Hence, captured data from the pre-
ceding devices in the boundary scan chain are lost and replaced by all-ones, and
data to succeeding devices are replaced by all-ones during Update-DR.
If ATmega64 is the only device in the scan chain, the problem is not visible.
XDIV, temp
; clear global interrupt enable
; set new prescale value
; no operation
; no operation
; no operation
; no operation
; no operation
; no operation
; no operation
; no operation
; clear global interrupt enable
ATmega64(L)
351

Related parts for ATMEga64L