ATMEga64L ATMEL Corporation, ATMEga64L Datasheet - Page 30

• Manufacturer Part Number: ATMEga64L
• Description: 8-bit AVR Microcontroller with 64K Bytes In-System Programmable Flash
• Manufacturer: ATMEL Corporation

XMEM Register
Description
MCU Control Register –
MCUCR
External Memory Control
Register A – XMCRA
30
ATmega64(L)
• Bit 7 – SRE: External SRAM/XMEM Enable
Writing SRE to one enables the External Memory Interface.The pin functions AD7:0,
A15:8, ALE, WR, and RD are activated as the alternate pin functions. The SRE bit over-
rides any pin direction settings in the respective data direction registers. Writing SRE to
zero, disables the External Memory Interface and the normal pin and data direction set-
tings are used.
• Bit 6 – SRW10: Wait State Select Bit
For a detailed description in non ATmega103 compatibility mode, see common descrip-
tion for the SRWn bits below (XMRA description). In ATmega103 compatibility mode,
writing SRW10 to one enables the wait state and one extra cycle is added during
read/write strobe as shown in Figure 14.
• Bit 7 – Res: Reserved Bit
This is a reserved bit and will always read as zero. When writing to this address location,
write this bit to zero for compatibility with future devices.
• Bit 6..4 – SRL2, SRL1, SRL0: Wait State Sector Limit
It is possible to configure different wait states for different external memory addresses.
The external memory address space can be divided in two sectors that have separate
wait-state bits. The SRL2, SRL1, and SRL0 bits select the split of the sectors, see Table
3 and Figure 11. By default, the SRL2, SRL1, and SRL0 bits are set to zero and the
entire external memory address space is treated as one sector. When the entire SRAM
address space is configured as one sector, the wait states are configured by the SRW11
and SRW10 bits.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
SRE
R/W
R
7
0
7
–
0
SRW10
SRL2
R/W
R/W
6
0
6
0
SRL1
R/W
R/W
SE
5
0
5
0
SRL0
SM1
R/W
R/W
4
0
4
0
SRW01
SM0
R/W
R/W
3
0
3
0
SRW00
SM2
R/W
R/W
2
0
2
0
SRW11
IVSEL
R/W
R/W
1
0
1
0
IVCE
R/W
R
0
0
0
–
0
2490G–AVR–03/04
MCUCR
XMCRA