ATMEga64L ATMEL Corporation, ATMEga64L Datasheet - Page 158

• Manufacturer Part Number: ATMEga64L
• Description: 8-bit AVR Microcontroller with 64K Bytes In-System Programmable Flash
• Manufacturer: ATMEL Corporation

Output Compare Register –
OCR2
Timer/Counter Interrupt Mask
Register – TIMSK
Timer/Counter Interrupt Flag
Register – TIFR
158
ATmega64(L)
The Output Compare Register contains an 8-bit value that is continuously compared
with the counter value (TCNT2). A match can be used to generate an Output Compare
interrupt, or to generate a waveform output on the OC2 pin.
• Bit 7 – OCIE2: Timer/Counter2 Output Compare Match Interrupt Enable
When the OCIE2 bit is written to one, and the I-bit in the Status Register is set (one), the
Timer/Counter2 Compare Match Interrupt is enabled. The corresponding interrupt is
executed if a Compare Match in Timer/Counter2 occurs, for example, when the OCF2
bit is set in the Timer/Counter Interrupt Flag Register – TIFR.
• Bit 6 – TOIE2: Timer/Counter2 Overflow Interrupt Enable
When the TOIE2 bit is written to one, and the I-bit in the Status Register is set (one), the
Timer/Counter2 Overflow Interrupt is enabled. The corresponding interrupt is executed if
an overflow in Timer/Counter2 occurs, for example, when the TOV2 bit is set in the
Timer/Counter Interrupt Flag Register – TIFR.
• Bit 7 – OCF2: Output Compare Flag 2
The OCF2 bit is set (one) when a Compare Match occurs between the Timer/Counter2
and the data in OCR2 – Output Compare Register2. OCF2 is cleared by hardware when
executing the corresponding interrupt handling vector. Alternatively, OCF2 is cleared by
writing a logic one to the flag. When the I-bit in SREG, OCIE2 (Timer/Counter2 Com-
pare Match Interrupt Enable), and OCF2 are set (one), the Timer/Counter2 Compare
match Interrupt is executed.
• Bit 6 – TOV2: Timer/Counter2 Overflow Flag
The bit TOV2 is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared
by hardware when executing the corresponding interrupt handling vector. Alternatively,
TOV2 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE2
(Timer/Counter2 Overflow Interrupt Enable), and TOV2 are set (one), the
Timer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set when
Timer/Counter2 changes counting direction at 0x00.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
OCIE2
OCF2
R/W
R/W
R/W
7
0
7
0
7
0
TOIE2
TOV2
R/W
R/W
R/W
6
0
6
0
6
0
TICIE1
ICF1
R/W
R/W
R/W
5
0
5
0
5
0
OCIE1A
OCF1A
R/W
R/W
R/W
4
0
4
0
4
0
OCR2[7:0]
OCIE1B
OCF1B
R/W
R/W
R/W
3
0
3
0
3
0
TOV1
TOIE1
R/W
R/W
R/W
2
0
2
0
2
0
OCF0
OCIE0
R/W
R/W
R/W
1
0
1
0
1
0
TOV0
TOIE0
R/W
R/W
R/W
0
0
0
0
0
0
2490G–AVR–03/04
OCR2
TIMSK
TIFR