ATMEga64L ATMEL Corporation, ATMEga64L Datasheet - Page 149

• Manufacturer Part Number: ATMEga64L
• Description: 8-bit AVR Microcontroller with 64K Bytes In-System Programmable Flash
• Manufacturer: ATMEL Corporation

Compare Output Mode and
Waveform Generation
Modes of Operation
Normal Mode
Clear Timer on Compare
Match (CTC) Mode
2490G–AVR–03/04
pin. The Data Direction Register bit for the OC2 pin (DDR_OC2) must be set as output
before the OC2 value is visible on the pin. The port override function is independent of
the Waveform Generation mode.
The design of the Output Compare pin logic allows initialization of the OC2 state before
the output is enabled. Note that some COM21:0 bit settings are reserved for certain
modes of operation. See “8-bit Timer/Counter Register Description” on page 155.
The Waveform Generator uses the COM21:0 bits differently in Normal, CTC, and PWM
modes. For all modes, setting the COM21:0 = 0 tells the Waveform Generator that no
action on the OC2 Register is to be performed on the next Compare Match. For com-
pare output actions in the non-PWM modes refer to Table 65 on page 156. For fast
PWM mode, refer to Table 66 on page 156, and for phase correct PWM refer to Table
67 on page 157.
A change of the COM21:0 bits state will have effect at the first Compare Match after the
bits are written. For non-PWM modes, the action can be forced to have immediate effect
by using the FOC2 strobe bits.
The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare
pins, is defined by the combination of the Waveform Generation mode (WGM21:0) and
Compare Output mode (COM21:0) bits. The Compare Output mode bits do not affect
the counting sequence, while the Waveform Generation mode bits do. The COM21:0
bits control whether the PWM output generated should be inverted or not (inverted or
non-inverted PWM). For non-PWM modes the COM21:0 bits control whether the output
should be set, cleared, or toggled at a Compare Match (see “Compare Match Output
Unit” on page 148).
For detailed timing information refer to Figure 68, Figure 69, Figure 70, and Figure 71 in
“Timer/Counter Timing Diagrams” on page 153.
The simplest mode of operation is the Normal mode (WGM21:0 = 0). In this mode the
counting direction is always up (incrementing), and no counter clear is performed. The
counter simply overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then
restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow Flag
(TOV2) will be set in the same timer clock cycle as the TCNT2 becomes zero. The
TOV2 flag in this case behaves like a ninth bit, except that it is only set, not cleared.
However, combined with the timer overflow interrupt that automatically clears the TOV2
flag, the timer resolution can be increased by software. There are no special cases to
consider in the Normal mode, a new counter value can be written anytime.
The Output Compare unit can be used to generate interrupts at some given time. Using
the Output Compare to generate waveforms in Normal mode is not recommended,
since this will occupy too much of the CPU time.
In Clear Timer on Compare or CTC mode (WGM21:0 = 2), the OCR2 Register is used to
manipulate the counter resolution. In CTC mode the counter is cleared to zero when the
counter value (TCNT2) matches the OCR2. The OCR2 defines the top value for the
counter, hence also its resolution. This mode allows greater control of the Compare
Match output frequency. It also simplifies the operation of counting external events.
The timing diagram for the CTC mode is shown in Figure 65. The counter value
(TCNT2) increases until a Compare Match occurs between TCNT2 and OCR2, and then
counter (TCNT2) is cleared.
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