ATMEga64L ATMEL Corporation, ATMEga64L Datasheet - Page 140

• Manufacturer Part Number: ATMEga64L
• Description: 8-bit AVR Microcontroller with 64K Bytes In-System Programmable Flash
• Manufacturer: ATMEL Corporation

Timer/Counter Interrupt Flag
Register – TIFR
Extended Timer/Counter
Interrupt Flag Register –
ETIFR
140
ATmega64(L)
(1)
• Bit 0 – OCIE1C: Timer/Counter1, Output Compare C Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Counter1 Output Compare C Match interrupt is enabled. The
corresponding Interrupt Vector (see “Interrupts” on page 59) is executed when the
OCF1C flag, located in ETIFR, is set.
Note:
• Bit 5 – ICF1: Timer/Counter1, Input Capture Flag
This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture
Register (ICR1) is set by the WGMn3:0 to be used as the TOP value, the ICF1 flag is set
when the counter reaches the TOP value.
ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. Alter-
natively, ICF1 can be cleared by writing a logic one to its bit location.
• Bit 4 – OCF1A: Timer/Counter1, Output Compare A Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Out-
put Compare Register A (OCR1A).
Note that a Forced Output Compare (FOC1A) strobe will not set the OCF1A flag.
OCF1A is automatically cleared when the Output Compare Match A Interrupt Vector is
executed. Alternatively, OCF1A can be cleared by writing a logic one to its bit location.
• Bit 3 – OCF1B: Timer/Counter1, Output Compare B Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Out-
put Compare Register B (OCR1B).
Note that a Forced Output Compare (FOC1B) strobe will not set the OCF1B flag.
OCF1B is automatically cleared when the Output Compare Match B Interrupt Vector is
executed. Alternatively, OCF1B can be cleared by writing a logic one to its bit location.
• Bit 2 – TOV1: Timer/Counter1, Overflow Flag
The setting of this flag is dependent of the WGMn3:0 bits setting. In Normal and CTC
modes, the TOV1 flag is set when the timer overflows. Refer to Table 61 on page 134
for the TOV1 flag behavior when using another WGMn3:0 bit setting.
TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is
executed. Alternatively, TOV1 can be cleared by writing a logic one to its bit location.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
1. This register contains flag bits for several Timer/Counters, but only Timer1 bits are
described in this section. The remaining bits are described in their respective timer
sections.
OCF2
R/W
R/W
7
0
7
–
0
TOV2
R/W
R/W
6
0
6
–
0
ICF1
ICF3
R/W
R/W
5
0
5
0
OCF1A
OCF3A
R/W
R/W
4
0
4
0
OCF1B
OCF3B
R/W
R/W
3
0
3
0
TOV1
TOV3
R/W
R/W
2
0
2
0
OCF3C
OCF0
R/W
R/W
1
0
1
0
OCF1C
TOV0
R/W
R/W
0
0
0
0
2490G–AVR–03/04
ETIFR
TIFR