ATMEga64L ATMEL Corporation, ATMEga64L Datasheet - Page 172

• Manufacturer Part Number: ATMEga64L
• Description: 8-bit AVR Microcontroller with 64K Bytes In-System Programmable Flash
• Manufacturer: ATMEL Corporation

Double Speed Operation
(U2X)
External Clock
Synchronous Clock Operation When synchronous mode is used (UMSEL = 1), the XCK pin will be used as either clock
172
ATmega64(L)
Table 74. Equations for Calculating Baud Rate Register Setting
Note:
Some examples of UBRR values for some system clock frequencies are found in Table
82 on page 192 to Table 85 on page 195.
The transfer rate can be doubled by setting the U2X bit in UCSRB. Setting this bit only
has effect for the asynchronous operation. Set this bit to zero when using synchronous
operation.
Setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively
doubling the transfer rate for asynchronous communication. Note however that the
Receiver will in this case only use half the number of samples (reduced from 16 to 8) for
data sampling and clock recovery, and therefore a more accurate baud rate setting and
system clock are required when this mode is used. For the Transmitter, there are no
downsides.
External clocking is used by the synchronous slave modes of operation. The description
in this section refers to Figure 80 for details.
External clock input from the XCK pin is sampled by a synchronization register to mini-
mize the chance of meta-stability. The output from the synchronization register must
then pass through an edge detector before it can be used by the Transmitter and
Receiver. This process introduces a two CPU clock period delay and therefore the max-
imum external XCK clock frequency is limited by the following equation:
Note that f
mended to add some margin to avoid possible loss of data due to frequency variations.
input (Slave) or clock output (Master). The dependency between the clock edges and
data sampling or data change is the same. The basic principle is that data input (on
RxD) is sampled at the opposite XCK clock edge of the edge the data output (TxD) is
changed.
Operating Mode
Asynchronous Normal
mode (U2X = 0)
Asynchronous Double
Speed mode (U2X = 1)
Synchronous Master
mode
BAUD Baud rate (in bits per second, bps)
f
UBRR Contents of the UBRRH and UBRRL Registers, (0 - 4095)
OSC
1. The baud rate is defined to be the transfer rate in bit per second (bps).
System Oscillator clock frequency
osc
depends on the stability of the system clock source. It is therefore recom-
BAUD
BAUD
BAUD
Equation for Calculating
Baud Rate
=
=
=
f
XCK
-------------------------------------- -
16 UBRR
---------------------------------- -
8 UBRR
---------------------------------- -
2 UBRR
(
(
(
<
f
f
f
f
---------- -
OSC
OSC
OSC
OSC
(1)
4
+
+
+
1
1
1
)
)
)
Equation for Calculating
UBRR
UBRR
UBRR
UBRR Value
=
=
=
----------------------- - 1
16BAUD
------------------- - 1
8BAUD
------------------- - 1
2BAUD
f
f
f
2490G–AVR–03/04
OSC
OSC
OSC
–
–
–