ATMEga64L ATMEL Corporation, ATMEga64L Datasheet - Page 257

• Manufacturer Part Number: ATMEga64L
• Description: 8-bit AVR Microcontroller with 64K Bytes In-System Programmable Flash
• Manufacturer: ATMEL Corporation

IDCODE; 0x1
SAMPLE_PRELOAD; 0x2
AVR_RESET; 0xC
BYPASS; 0xF
2490G–AVR–03/04
The active states are:
•
•
•
Optional JTAG instruction selecting the 32-bit ID-Register as data register. The ID-Reg-
ister consists of a version number, a device number and the manufacturer code chosen
by JEDEC. This is the default instruction after Power-up.
The active states are:
•
•
Mandatory JTAG instruction for taking a snap-shot of the input/output pins without
affecting the system operation, and pre-loading the output latches. However, the output
latches are not connected to the pins. The Boundary-scan Chain is selected as data
register.
The active states are:
•
•
•
The AVR specific public JTAG instruction for forcing the AVR device into the Reset
mode or releasing the JTAG Reset source. The TAP controller is not reset by this
instruction. The one bit Reset Register is selected as data register. Note that the reset
will be active as long as there is a logic “one” in the Reset Chain. The output from this
chain is not latched.
The active states are:
•
Mandatory JTAG instruction selecting the Bypass Register for Data Register.
The active states are:
•
•
Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain.
Shift-DR: The internal scan chain is shifted by the TCK input.
Update-DR: Data from the scan chain is applied to output pins.
Capture-DR: Data in the IDCODE Register is sampled into the Boundary-scan
Chain.
Shift-DR: The IDCODE scan chain is shifted by the TCK input.
Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain.
Shift-DR: The Boundary-scan Chain is shifted by the TCK input.
Update-DR: Data from the Boundary-scan Chain is applied to the output latches.
However, the output latches are not connected to the pins.
Shift-DR: The Reset Register is shifted by the TCK input.
Capture-DR: Loads a logic “0” into the Bypass Register.
Shift-DR: The Bypass Register cell between TDI and TDO is shifted.
ATmega64(L)
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