ATMEga64L ATMEL Corporation, ATMEga64L Datasheet - Page 189

no-image

ATMEga64L

Manufacturer Part Number
ATMEga64L
Description
8-bit AVR Microcontroller with 64K Bytes In-System Programmable Flash
Manufacturer
ATMEL Corporation
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEga64L-16AU
Manufacturer:
ROHM
Quantity:
40 000
Part Number:
ATMEga64L-8AC
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
ATMEga64L-8AI
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
ATMEga64L-8AI
Manufacturer:
ALTERA
0
Part Number:
ATMEga64L-8AI
Manufacturer:
AT
Quantity:
20 000
Part Number:
ATMEga64L-8AJ
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
ATMEga64L-8AQ
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
ATMEga64L-8AQ
Manufacturer:
AT
Quantity:
20 000
Part Number:
ATMEga64L-8AU
Manufacturer:
ATMEL
Quantity:
4 000
Part Number:
ATMEga64L-8AU
Manufacturer:
ATMEL
Quantity:
451
Part Number:
ATMEga64L-8AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
ATMEga64L-8MI
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
ATMEga64L-8MU
Quantity:
113
Part Number:
ATMEga64L-8MUR
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
ATMEga64L8AJ
Manufacturer:
ATMEL
Quantity:
6 973
USART Control and Status
Register C – UCSRC
2490G–AVR–03/04
(1)
do not contain data to be transmitted. When disabled, the Transmitter will no longer
override the TxD port.
• Bit 2 – UCSZ2: Character Size
The UCSZ2 bits combined with the UCSZ1:0 bit in UCSRC sets the number of data bits
(Character Size) in a frame the Receiver and Transmitter use.
• Bit 1 – RXB8: Receive Data Bit 8
RXB8 is the ninth data bit of the received character when operating with serial frames
with nine data bits. Must be read before reading the low bits from UDR.
• Bit 0 – TXB8: Transmit Data Bit 8
TXB8 is the ninth data bit in the character to be transmitted when operating with serial
frames with nine data bits. Must be written before writing the low bits to UDR.
Note:
• Bit 7 – Reserved Bit
This bit is reserved for future use. For compatibility with future devices, this bit must be
written to zero when UCSRC is written.
• Bit 6 – UMSEL: USART Mode Select
This bit selects between asynchronous and synchronous mode of operation.
Table 77. UMSEL Bit Settings
• Bit 5:4 – UPM1:0: Parity Mode
These bits enable and set type of parity generation and check. If enabled, the Transmit-
ter will automatically generate and send the parity of the transmitted data bits within
each frame. The Receiver will generate a parity value for the incoming data and com-
pare it to the UPM0 setting. If a mismatch is detected, the UPE flag in UCSRB will be
set.
Table 78. UPM Bits Settings
Bit
Read/Write
Initial Value
UPM1
1. This register is not available in ATmega103 compatibility mode.
UMSEL
0
0
1
1
0
1
R/W
7
0
UMSEL
R/W
6
0
UPM0
Mode
Asynchronous Operation
Synchronous Operation
0
1
0
1
UPM1
R/W
5
0
UPM0
R/W
Parity Mode
Disabled
Reserved
Enabled, Even Parity
Enabled, Odd Parity
4
0
USBS
R/W
3
0
UCSZ1
R/W
2
1
ATmega64(L)
UCSZ0
R/W
1
1
UCPOL
R/W
0
0
UCSRC
189

Related parts for ATMEga64L