ISL6551EVAL1 Intersil, ISL6551EVAL1 Datasheet - Page 10

• Manufacturer Part Number: ISL6551EVAL1
• Description: EVALUATION BOARD ISL6551
• Manufacturer: Intersil

Specifications of ISL6551EVAL1

• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Isolated
• Voltage - Output: 3.3V
• Current - Output: 60A
• Voltage - Input: 36 ~ 75V
• Regulator Topology: Buck
• Frequency - Switching: 470kHz
• Board Type: Fully Populated
• Utilized Ic / Part: ISL6551
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -

Converter Design
This section presents a step-by-step design procedure for a
48V-to-3.3V, 200W, 470kHz with 88% efficiency converter
using both ISL6551 and ISL6550 for telecom applications
(i.e V
secondary-referenced, peak current-mode control, and both
ZVS full bridge and current doubler topologies.
For simplicity, all calculations in this section neglect the
transitions shown in Figure 5. The worst case current
waveforms are used even in the INV_LOW DRIVE scheme,
unless otherwise stated.
Select Synchronous DRIVE Scheme
The INV_LOW DRIVE scheme for synchronous rectification
is employed in the reference design. This scheme induces
less conduction losses in the synchronous FETs than both
INV_SYNC and SYNC DRIVE schemes, which can be
explained with a few equations (EQ. 1- 6). The terms used in
all equations are defined later in the paper, unless otherwise
stated in the text.
The power dissipation is the same in the active (transfer)
period but different in the freewheeling period for the three
drive schemes. In both INV_SYNC and SYNC DRIVE
schemes, only one synchronous FET is turned on carrying
all the load current during the freewheeling period. The
conduction losses of each leg in the freewheeling period can
be approximated with EQ. 3:
In the INV_LOW DRIVE scheme, both synchronous FETs
are turned on and each one carries a portion of the load
current during the freewheeling period. The power
dissipation of each leg in this period is reduced to EQ. 4:
Comparing EQ. 3 to EQ. 4, we note that the INV_LOW
scheme induces less power dissipation in the synchronous
FETs by an amount of EQ. 5:
In addition, the INV_LOW scheme also helps cut down the
conduction losses in the primary FETs since the primary has
less reflected secondary current, which decreases with the
difference between IQ1 and IQ2, as shown in EQ. 6:
Psynfetfr
∆Psynfetfr
Io
Psynfetfr
IQ1
2
2
=
IN
+
(
=36V-to-75V). The converter is designed with
IQ1
IQ2
=
=
2
+
=
≤
(
Io
IQ2
IQ1
IQ1
2 IQ1 IQ2
2
•
•
)
2
2
2


1 D
------------ -
+
+
=
–
IQ2
2
IQ2
•
IQ1


2
2
•
)
2
+
Rdsonsyn
•
•
+
2 IQ1 IQ2


(
10
IQ2
1 D
------------ -
1 D
•
–
2
–
2


+
)
•
•
•
2 IQ1 IQ2
Rdsonsyn
Rdsonsyn
•
•
Application Note 1002
(EQ. 3)
(EQ. 4)
(EQ. 5)
(EQ. 1)
(EQ. 2)
Although the INV_LOW scheme is a better choice from the
power dissipation standpoint, the user should pay special
attention to the impact of having on overlap between both
synchronous FETs during the freewheeling period in current
share, light load, start up, and turn-off operations. Some
discussions are presented in the EXPERIMENTAL
RESULTS section.
Select Switching Frequency and Define Maximum
Available Duty Cycle
Several things are considered when selecting an appropriate
switching frequency for a particular application. The size of
the converter (limited by sizes of magnetics components),
the overall losses of magnetics components, the switching
losses of power MOSFETs, the desired efficiency, the
transient response, and the maximum achievable duty cycle
are all considerations. An iterative process is required,
monitoring changes of the above parameters, to obtain an
optimum switching frequency for a particular application.
Users can use equations presented in this paper to design a
MathCAD worksheet, which will help obtain a rough idea of
the range of optimum frequencies for their applications. Note
that the higher the switching frequency is, the higher the loop
bandwidth (typical 1/10 or higher of the switching frequency)
can be realized, but the lower the maximum duty cycle is
available.
In the initial design of the evaluation board, these
parameters are pre-selected: Fsw=250kHz=Fclock/2,
t
duty cycle then can be calculated using EQ. 7
(Dmaxav=85%). The duty cycle defined in this application
note is the ratio of the ON-time interval of a lower FET to one
clock period.
Define Turns Ratio
The primary-to-secondary turns ratio of the main transformer
should be chosen as high as possible without exceeding the
maximum available duty cycle (Dmaxav=0.85) at the
minimum line (Vinmin=36V, or the input UV setpoint) and the
rated load (Io=60A) situation. The higher the turns ratio is,
the less the load current is reflected to the primary side, and
the less the power losses are induced by the primary
MOSFETs. The maximum allowable turns ratio can be
calculated with EQ. 8 (Nmax=3.79).
Ip
DEAD
Dmaxav
Dmaxav
≈
Is
---- -
N
=200ns, and t
=
IQ1 IQ2
-------------------------- -
=
=


-------------------------------------------------------------------------------------------------------------


2N
1
Vinmin Rdsonpri
–
2
–
•
t
----------------------------------------------- -
DEAD
(
Vomax
RESDLY
–
Fclock
–
t
RESDLY
+
Vmisc
=100ns. The maximum available
•


Io
---- -
N
+


Vsynfet
–
Vsynfet N
) N
•
•
(EQ. 8)
(EQ. 7)
(EQ. 6)