ISL6551EVAL1 Intersil, ISL6551EVAL1 Datasheet - Page 23

• Manufacturer Part Number: ISL6551EVAL1
• Description: EVALUATION BOARD ISL6551
• Manufacturer: Intersil

Specifications of ISL6551EVAL1

• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Isolated
• Voltage - Output: 3.3V
• Current - Output: 60A
• Voltage - Input: 36 ~ 75V
• Regulator Topology: Buck
• Frequency - Switching: 470kHz
• Board Type: Fully Populated
• Utilized Ic / Part: ISL6551
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -

The dead time and the resonant delay, with 2V as the turn-on
threshold of primary switches, of one converter is summarized
in Table 3. The real delays at the primary switches are shorter
than the “delays” set at the ISL6551 due to long propagation
delays of falling edges of both upper and lower drive signals.
Furthermore, the leakage inductances of pulse transformers
also would induce additional propagation delays depending on
the drive current through it. The higher the energy through the
pulse transformer is, the longer the delay would be.
FIGURE 20. RESONANT DELAY AT LOWER FET. CHANNEL
FIGURE 21. DEAD TIME AT LOWER FET. CHANNEL 1:
Resonant Delay
Dead Time
DELAY
TABLE 4. RESONANT DELAY AND DEAD TIME
1: LOWER DRIVE SIGNAL; CHANNEL 2 & 3:
UPPER DRIVE SIGNALS
LOWER DRIVE SIGNAL; CHANNEL 2 & 3:
UPPER DRIVE SIGNALS
3
1
AT SWITCH’S GATE
157 ns
32 ns
23
2
AT ISL6551
186 ns
36 ns
Application Note 1002
1
2
3
The synchronous drive signals are the inverting version of
both lower drive signals with little propagation delays. The
turn-on gate resistors, R23 and R33, soften the rising edge
of the lower drive signals, while the diodes, D5 and D19,
reduce their falling edge delay. Meanwhile, the diodes, D1
and D4, minimize the turn-off delay of the synchronous drive
signals, while the resistors, R3 and R18, increase their turn-
on delay. As shown in Figure 24, the synchronous FET is
turned off/on (Channel 2) whenever its corresponding lower
switch is turned on/off (Channel 3). There is no overlap
between these two drive signals. Hence, shoot-through
currents between the secondary winding and the
synchronous FETs are eliminated.
FIGURE 22. RESONANT DELAY AT ISL6551. CHANNEL 1:
FIGURE 23. DEAD TIME AT ISL6551. CHANNEL 1: LOWER
LOWER DRIVE SIGNAL; CHANNEL 2 & 3:
UPPER DRIVE SIGNALS
DRIVE SIGNAL; CHANNEL 2 & 3: UPPER
DRIVE SIGNALS
3
1
1
2
2
3