ISL6551EVAL1 Intersil, ISL6551EVAL1 Datasheet - Page 37

• Manufacturer Part Number: ISL6551EVAL1
• Description: EVALUATION BOARD ISL6551
• Manufacturer: Intersil

Specifications of ISL6551EVAL1

• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Isolated
• Voltage - Output: 3.3V
• Current - Output: 60A
• Voltage - Input: 36 ~ 75V
• Regulator Topology: Buck
• Frequency - Switching: 470kHz
• Board Type: Fully Populated
• Utilized Ic / Part: ISL6551
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -

In addition to the above loop measurement, the following
presents some modeling results using the simplified loop
system including the high-frequency correlation term as
discussed in the Control Loop Design section on page 16.
The feedback compensation and the differential amplifier
stages are verified with the 350 Venable System, as shown
in Figures 82 and 83. They are well matched with the
theoretical results except that the phase at the differential
amplifier stage is smaller at above 100kHz than is expected.
In addition, each TAIYO YUDEN capacitor is characterized
with 100uF capacitance in series with 1.8m
6nH ESL as defined in EQ. 61, which is also verified with the
Venable System.
Thus, the only variable is the plant, i.e., the load and the
power train.
Zcap jω
-10
-15
-20
-25
-30
-35
-40
-45
-50
-55
-60
-10
-20
-30
-40
-50
-60
-70
-80
-90
(
10
1.0E+02
40
30
20
10
-5
1.0E+02 1.0E+03 1.0E+04 1.0E+05 1.0E+06
5
0
0
)
=
FIGURE 82. COMPENSATION STAGE
FIGURE 83. DIFFERENTIAL STAGE
-------------------------------- -
jω100x10
1.0E+03
1
Fequency (Hz)
Fequency (Hz)
–
Frequency (Hz)
Frequency (Hz)
6
1.0E+04
+
1.8x10
37
1.0E+05
–
3
+
jω6x10
1.0E+06
Ω
–
ESR and
9
Measured
Gain
Measured
Phase
Model
Gain
Model
Phase
Application Note 1002
Measured
Gain
Measured
Phase
Model
Gain
Model
Phase
(EQ. 61)
FIGURE 86. PLANT RESPONSE FOR 38A “PURE” RESISTIVE
-100
-120
-140
-160
-180
-100
-120
-140
-160
-180
-200
-220
-240
180
160
140
120
100
-20
-40
-60
-80
-20
-40
-60
-80
80
60
40
20
20
1.0E+02
1.0E+02
FIGURE 84. OUTPUT CAPACITOR MODELING
0
0
-10
-20
-30
90
80
70
60
50
40
30
20
10
1.0E+0
0
2
LOAD
1.0E+03
1.0E+03
FIGURE 85. OUTPUT LOAD
1.0E+0
Fequency (Hz)
Fe que ncy (Hz)
3
Frequency (Hz)
Frequency (Hz)
Frequency (Hz)
Frequency (Hz)
1.0E+04
1.0E+04
1.0E+0
4
1.0E+05
1.0E+05
1.0E+0
5
1.0E+06
1.0E+06
1.0E+0
6
Measured
Gain
Measured
Phase
Model
Gain
Model
Phase
Measured
Gain
Measured
Phase
Model
Gain
Model
Phase
Measured
Gain
Measured
Phase
Model
Gain
Model
Phase