ISL6551EVAL1 Intersil, ISL6551EVAL1 Datasheet - Page 18

• Manufacturer Part Number: ISL6551EVAL1
• Description: EVALUATION BOARD ISL6551
• Manufacturer: Intersil

Specifications of ISL6551EVAL1

• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Isolated
• Voltage - Output: 3.3V
• Current - Output: 60A
• Voltage - Input: 36 ~ 75V
• Regulator Topology: Buck
• Frequency - Switching: 470kHz
• Board Type: Fully Populated
• Utilized Ic / Part: ISL6551
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -

• Heavy copper traces should be connected to the bias pins
• The copper routings from the drivers to the FETs should
• In the MLFP package, the pad underneath the center of
Shutdown Timing Diagram of the Converter
INPUT UV (1): With all the biases powered up and the
mechanical switch at the PEN pin turned on, the converter is
enabled after the input reaches its turn-on threshold (34.3V).
The output voltage rises to its regulation point following the
soft start. The soft start capacitor continues to be charged up
to the clamping voltage (Vclamp). The DCOK is pulled low
indicating “GOOD” once the output reaches within -3% of the
set point.
ENABLE (2): When the PEN pin is pulled low, the soft start
capacitor is discharged very quickly and all the drivers are
disabled. The DCOK is pulled high indicating “FAULT” when
(INTERNAL)
connected to the net before the input capacitors, i.e., the
input return pinouts.
(VDD, VDDP1, VDDP2) and the ground pins (VSS and
PGND) for heat spreading.
be kept short and wide, especially in very high frequency
applications, to reduce the inductance of the traces so that
the drive signals can be kept clean, no bouncing.
the IC is a “floating” thermal substrate. The PCB “thermal
ILIM_OUT
ON/OFF
(START)
(+/-3, 5%)
ENABLE
LATSD
START
DCOK
SOFT
(PEN)
V
VDD
OUT
V
IN
34.3V
THRESHOLD
TURN-ON
INPUT
1
CONVERTER
DISABLED
PKILIM
> BGREF
18
2
FIGURE 19. SHUTDOWN TIMING DIAGRAM OF THE CONVERTER
OVERCURRENT
(
WITH UV DELAY
V
3
OUT
< 1-8.33%)
LATCHED
W/70ms
DELAY
LATCH
RESET
Application Note 1002
BEYOND
1+/-8.33%
V
LATCHED
OUT
4
FAULT
PKILIM < BGREF
LATCH
RESET
• For additional tips, please refer to “PCB Design Guidelines
the output voltage is discharged below -5% of the set point.
When the PEN pin is released, a soft start is initiated.
OVER CURRENT (3): If the output of the converter is over
loaded, i.e, the PKILIM is above the bandgap reference
(BGREF), the soft start capacitor is discharged quickly and
all the drivers are turned off. Once the output voltage is
below -8.33% of the regulation point, the capacitor of the
under-voltage delay set at ISL6550 is then charged up, and
the START is latched when the voltage at the capacitor
reaches 5V. The ISL6551 controller is quickly shut down by
the START. If the over load is removed and the converter can
return to normal operation within the under-voltage delay
land” design for this exposed die pad should include
thermal vias that drop down and connect to buried copper
plane(s). This combination of vias for vertical heat escape
and buried planes for heat spreading allows the MLFP to
achieve its full thermal potential. It is recommended to
connect this pad to the low noise copper plane Vss.
For Reduced EMI” [5].
GOOD
MASTER
OV (4.0V)
5
LATCHED
LATCH
CANNOT
BE RESET
THRESHOLD
TURN-ON
VDD
LATCH
RESET BY
VDD
9.6V
6
THRESHOLD
TURN-OFF
VDD
8.6V
7
THRESHOLD
TURN-OFF
INPUT
33.3V
8