ISL6551EVAL1 Intersil, ISL6551EVAL1 Datasheet - Page 15

• Manufacturer Part Number: ISL6551EVAL1
• Description: EVALUATION BOARD ISL6551
• Manufacturer: Intersil

Specifications of ISL6551EVAL1

• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Isolated
• Voltage - Output: 3.3V
• Current - Output: 60A
• Voltage - Input: 36 ~ 75V
• Regulator Topology: Buck
• Frequency - Switching: 470kHz
• Board Type: Fully Populated
• Utilized Ic / Part: ISL6551
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -

secondary winding, as illustrated in EXPERIMENTAL
RESULTS, prior to turn off the synchronous FET, help to
achieve ZVT for the synchronous FETs at turn off. To
achieve ZVT as discussed in previous lines, the synchronous
FET drivers however should have high current capability with
little propagation delays such as MICREL 9A MIC4421
inverting drivers or better. The conduction losses and
reverse recovery losses of body diodes of the synchronous
FETs at turn on or off are not discussed here, but they do
show up in Figure 35.
Note that the drivers with high current capability can shorten
the transition time and reduce the switching losses.
The driver losses due to the gate charge of the MOSFETs
should be investigated thoroughly to prevent over stressing.
The switching losses of both primary and secondary drivers
and its corresponding average driver current due to the gate
charge can be estimated with EQs. 46 and 47, respectively,
where Qg and V
Define Requirements of Main Transformer
This section summarizes major design requirements of the
main transformer at the switching frequency.
The turns ratio of the transformer is derived from EQ. 9
while EQ. 32 defines the peak current through the primary
winding. The RMS current through the primary winding is
defined in EQ. 48.
The current through the secondary winding is only half of the
load, and its RMS currents in both transfer and freewheeling
periods can be defined by EQs. 49 and 50, respectively. The
overall RMS current through the secondary winding can be
calculated with EQ. 51.
The magnetizing inductance (Lmag) is determined by the
number of turns of primary winding, the core geometry, and
the air gap. The Lmag however should not be designed too
low. If it is too low, high power dissipation will be introduced
in the primary switches, and too much ramp will be added to
Idr
Pdr
Iprms
Isrms
Isrmstr
Isrmsfr
=
=
----------- - Vcc Fsw
V
Qg
----------- - Vcc
V
=
=
GS
Qg
GS
=
=
•
2 Iprirms
Isrmstr
•
•






Io
------- -
4
Io
---- -
2
2
GS
•
+
2
+
2
•
--------------------- -
2 2 D
dI
------- -
12
+
are defined in the MOSFET datasheet.
(
Fsw
2
Isrmsfr
dI


–
•
D
)


2
2
+
15
dI
------------------------------
12 2 D
2
(
(
1 D
–
–
)
)
2
2


•
(
1 D
–
)
Application Note 1002
(EQ. 46)
(EQ. 47)
(EQ. 48)
(EQ. 49)
(EQ. 50)
(EQ. 51)
the current ramp signal, which makes the supply look
voltage mode. A reasonable small Lmag can assist ZVS and
decrease any noise sensitivity problems. Around 100uH is a
start point for telecom brick applications. In addition, it is
recommended to have a small gap in the transformer
stabilizing the magnetizing inductance so that the
magnetizing current can be within a controllable range.
The leakage inductance is not an issue in the design. In fact,
it is part of the commutating inductance to assist ZVS using
its stored energy. Too much leakage inductance however will
lower the effective duty cycle, resulting in a lower turns ratio.
The primary-to-secondary capacitance should be minimized
since it robs energy from the ZVS elements increasing the
resonant time and decreasing the maximum available duty
cycle and the ZVS load range.
As far as the size of the transformer is concerned, it varies
with applications. In the reference design, the transformer is
limited to less than 0.5 inch height, being able to fit into a
telecom half brick.
Determine Commutating Inductance
The required external commutating inductance is
determined by the slower transition (from passive to active
period) since the commutating inductance stores the least
energy for ZVS. The ZVS condition is that the energy stored
in the commutating inductance, defined in EQ. 52, should be
greater than the energy stored in the primary capacitance,
defined in EQ. 53. Thus, the required external commutating
inductance can be roughly estimated with EQ. 54. Refer to
[1] for detailed discussion.
Note that the output capacitance (Coss) of the MOSFET
varies with the drain to source voltage, and the primary
current (Ip) at the end of the freewheeling period determined
by the turns ratio and current distribution factor F
external commutating inductor however would be better
defined in the real circuits by trial and errors.
Control Loop Design
The secondary-referenced, peak current control is
implemented in the converter design. Two pulse
transformers pass the PWM information of the full-bridge
controller (ISL6551) to two high current half-bridge drivers
(HIP2100s) in the primary. A current transformer is to feed
the primary current information to the full-bridge controller,
as a feed-forward loop. The control loop is closed by an error
amplifier, for loop compensation purpose, cascaded with a
E
E
L
L
C
ext
=
=
<
1
-- - L
2
1
-- - 2Coss
2
Vin
------------------------------------------------------------- - L
(
(
ext
2
(
•
Imag
+
(
2 Coss
L
+
k
•
)
Cp
•
+
(
Ip
Imag
) Vin
•
)
2
+
Cp
+
2
Ip
)
–
)
2
k
DIST
(EQ. 52)
(EQ. 53)
(EQ. 54)
. The