ISL6551EVAL1 Intersil, ISL6551EVAL1 Datasheet - Page 22

• Manufacturer Part Number: ISL6551EVAL1
• Description: EVALUATION BOARD ISL6551
• Manufacturer: Intersil

Specifications of ISL6551EVAL1

• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Isolated
• Voltage - Output: 3.3V
• Current - Output: 60A
• Voltage - Input: 36 ~ 75V
• Regulator Topology: Buck
• Frequency - Switching: 470kHz
• Board Type: Fully Populated
• Utilized Ic / Part: ISL6551
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -

Debugging TIPS
This section discusses some easy ways to bring up the
power train in the least amount of time.
Before/After Build
Apply Biases with Current and Voltage Limiting
Before applying the input voltage to the converter, a quick
check of all control circuits is always the first step.
10. Check if the timing of the synchronous signals is
Power Up Slowly with Current and Voltage Limiting
1. Before building the board, it is wise to check if all
2. After the build, check if pin 1 of all ICs is placed properly.
1. Use Table 1 on page 15 of the ISL6551 datasheet design
2. Disable anything that prevents both ISL6551 and
3. In series forward diodes with the bias lines so that all ICs
4. Apply biases with current limiting.
5. Check if both DC and AC voltage levels of each ISL6550
6. Check if both DC and AC voltage levels of each ISL6551
7. Check if a nice sawtooth is in CT pin and equal pulse
8. Check if both DC and AC voltage levels of drive signals of
9. Check if the delays such as Dead Time, Resonant Delay,
1. If possible, disconnect the secondary winding from the
2. Connect the secondary winding back to the circuit and
3. Increase the input voltage slowly with input and output
magnetics components such as current transformer,
main transformer, output inductors, input inductor, and
commutating inductor are designed properly using
magnetics design tools or waveforms across the
magnetics method. In addition, all components,
especially the power train components, should be
checked if their power/thermal derating guidelines are
met.
checklist.
ISL6550 from free running. In the reference design,
disconnecting the resistor (R6) between the START pin of
the ISL6550 and the ON/OFF pin of ISL6551 will allow
both chips to be free running.
will not be damaged by reverse biasing. The reference
design has built-in diodes.
pinout are correct. No noises and no over stressed.
pinout are correct. No noises and no over stressed.
width is between upper drive signals.
bridge FETs and synchronous FETs are correct. No
noises and no over stressed.
and LEB Delay are designed properly.
designed properly. No shoot through.
secondary side, then increase the input voltage slowly.
Fix the primary timing until no (very low) current is drawn
from the input line. And check if the magnetizing current
is in a proper level.
disable the synchronous drivers such that the current
conducts only through the body diodes of the
synchronous FETs.
current limiting and monitor the current through the main
22
Application Note 1002
Experimental Results
The evaluation board is intended to test the ISL6551 in a
200W half brick form factor. The specification of this
converter is summarized at the end of this paper. Most of the
converter circuitries are placed in the central 2.50”x2.45”
area and limited within 0.5” height, and all unnecessary
components such as test point connectors and Input/Output
connectors are placed beyond the center.This DC/DC
converter accepts a wide range input, 36V to 75V, and
generates a wide range output, 2.64V to 3.63V with
31.918mV step and 60A full load. An ultra high efficiency,
88% efficiency at 3.3V fully loaded output, has been
achieved. In the following sections, some critical aspects of
the converter are examined with detailed experimental data.
Drive Signal Timing
The drive signals are taken when the ISL6551 is free running,
which can be done by removing the input line and R6 that
connects to the START pin of the ISL6550. The resonant delay
to turn on the lower switch after the corresponding upper switch
is turned off, as shown in Figure 20, helps achieve zero-voltage
switching (ZVS). The dead time to turn on the upper FET after
the corresponding lower switch is turned off, as shown in
Figure 21, helps eliminate the shoot-through currents
through the primary switches during switching transitions.
Figures 22 and 23 show the resonant delay and the dead
time set at the ISL6551 prior to be processed through pulse
transformers (T3 andT5) and bridge drivers (Intersil HIP2100).
4. If the converter is not stable, use a low ESR ceramic
5. Enable the synchronous drivers. If the timing is not set
6. Check the current ramp signal at the ISENSE pin of
7. Tune up. Design a proper resonant delay by programming
transformer or the current ramp signal that is fed into the
ISL6551. No asymmetric behaviors should be seen and
ten percent of load is a good start point.
capacitor (say 0.1uF) at the feedback network to cut down
the cut-off frequency until the converter becomes stable.
Or use the simplified model in Figure 18 to design a low
cut-off frequency system loop. Later, optimize the loop
with a tool.
properly, shoot-through currents between the secondary
winding and the synchronous FETs would be induced
and affect the converter’s performance, especially in light
load conditions. Start with some load (10% rated load)
and work backward.
ISL6551 and see if a longer blanking time is required.
the R_RESDLY resistor and changing (if possible) the
ZVS elements such as, the magnetizing inductance, the
leakage inductance, any external commutating inductor,
the output capacitance of bridge FETs, and any external
primary capacitance. Note that any loop that is used to
measure the primary current can induce additional
commutating inductance, depending upon the enclosed
air area, and extends the ZVS load range. For instance,
5.0” of 14AWG wire can contribute as much as 80nH
inductance.