ISL6551EVAL1 Intersil, ISL6551EVAL1 Datasheet - Page 9

• Manufacturer Part Number: ISL6551EVAL1
• Description: EVALUATION BOARD ISL6551
• Manufacturer: Intersil

Specifications of ISL6551EVAL1

• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Isolated
• Voltage - Output: 3.3V
• Current - Output: 60A
• Voltage - Input: 36 ~ 75V
• Regulator Topology: Buck
• Frequency - Switching: 470kHz
• Board Type: Fully Populated
• Utilized Ic / Part: ISL6551
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -

• The output voltage is sensed by the OVUVSEN, and the
output error should include VREF5 error and external
resistor divider error as well as the internal buffer offset. In
the reference design, the output voltage can be
programmed from 2.64V to 3.63V with 31.918mV step and
+/-3% statics error over full operating conditions.
OV-UV windows is centered around the BDAC voltage and
can be programmed with the OVUVTH pin from +/-5% to
NOTE: Pin numbers in the diagram refer to the SOIC package.
R2
R3
R1
OVUVSEN
OVUVTH
VOPOUT
DACLO
DACHI
VOPM
UVD
PEN
NOTE: S input dominates Q
VOPP
Note: UV/OV
hysteresis = 10%
UV
PEN
VID4
VID0
VID3
VID2
VID1
2A
POR
OV
10
16
19
13
14
11
12
15
3
2
4
8
9
(each VID pin)
Opamp
10uA to 5V
THRESHOLD
PROGRAM
10uA to 5V
R
S
FAULT
LATCH
-
+
9
Q
PEN
POR
Q: H = Fault;
Q
PEN
POR
Q
UV
L = No Fault
FIGURE 14. ISL6550 INTERNAL STRUCTURE
Application Note 1002
NOTE: No latch in 2B
Note: UV/OV
hysteresis = 40%
VREF5
2B
OV
UV
5
5V
UV/OV hysteresis
See Note
below
UVLOCKOUT
(POR)
UVDELAY
Buffered
5V REF
VCC
GND
1
6
PEN
POR
UVD
• PEN is connected to a mechanical switch to turn on/off the
• PGOOD provides an indication if the output voltage is
OV
PEN
POR
OV
UV
+/-40% about the BDAC voltage. In the reference design,
the over/under voltage window is set at +/-8.33%.
converter manually. It is also controlled by the circuitries
that monitor the input voltage level and the thermal
condition of the converter.
within over/under voltage limits (+/-8.33%).
PEN: H = Enable; L = Disable
POR: H = VDD too low; L = VDD OK
OV: H = Over-Voltage; L = OK
UV: H = Under-Voltage; L = OK
UVD: H = UV Delay timed out; L = no time-out
LOGIC BLOCK
see 2A, 2B, 2C below
UVD
PEN
NOTE: S input dominates Q
Note: UV/OV
hysteresis = 10%
UV
2C
POR
OV
PEN
R
S
FAULT
LATCH
Q
PEN
POR
Q: H = Fault;
Q
POR
OV
UV
L = No Fault
17
18
20
7
START
PGOOD
UVDLY
BDAC
R4
R5