ISL6551EVAL1 Intersil, ISL6551EVAL1 Datasheet - Page 11

• Manufacturer Part Number: ISL6551EVAL1
• Description: EVALUATION BOARD ISL6551
• Manufacturer: Intersil

Specifications of ISL6551EVAL1

• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Isolated
• Voltage - Output: 3.3V
• Current - Output: 60A
• Voltage - Input: 36 ~ 75V
• Regulator Topology: Buck
• Frequency - Switching: 470kHz
• Board Type: Fully Populated
• Utilized Ic / Part: ISL6551
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -

where Vsynfet = Io x Rdsonsyn/2 is the channel drop of the
synchronous FETs at half of the load (assuming that the
output load is split evenly into both synchronous FETs during
the freewheeling period), Vomax is the maximum output
voltage (3.63V), and Vmisc is the sum of the miscellaneous
voltage drops including contact resistance, winding
resistance, PCB copper resistance. The initial guess of
Vmisc is 0.3V for having a safe margin. If the load (Io)
conducts through only one synchronous FET during the
freewheeling period, then EQ. 8 can be simplified to EQ. 9
(Nmax=3.77):
With the assumptions of Rdsonpri=25 x1.2mΩ (Tj=50
and Rdsonsyn=1.125x1.13mΩ (Tj=50
Nmax=3.77. Since the size and height of the converter are
limited to that of a telecom half brick, a planar transformer
with a low number of turns on both the primary and
secondary sides is required. Therefore, 7/2 and 11/3 turns
ratio are preferred choices. A transformer with 7 primary
turns and 2 secondary turns has been used in the reference
design due to the availability of magnetic cores in stock. In
fact, a transformer with 11/3 turns ratio is generally
recommended.
Output Filter Design (Current Doubler)
The output L-C filter is normally defined based on
requirements of the output ripple voltage (70mV) and the
transient response (dVtr=150mV). In general, if the
requirement of the transient response is met, then the output
ripple voltage will be within the limit.
As a rule of thumb, the overall ripple current (dIo) should be
no more than 20% of the rated load, and the output inductor
value (for each one) can be defined by EQ. 10:
The ripple current (dI) through each inductor can be
calculated with EQ. 11:
The requirement of the transient response is the major factor
of defining the maximum overall ESR of the output
capacitors in EQ. 12. Note that this converter is designed to
meet 150mV transients (dip/overshoot) for a 25% rated load
step (ESR < 10mΩ).
dI
Lo
ESR
Dmaxav
=
=
(
-------------------------------------------------------------------------- -
<
2
----------------------------------------------------------------------------------- -
Vo
--------------
Istep
dVtr
•
(
+
=
Vo
2 V
---------------------------------------------------------------------------------------------------------- -
2
• synfet
Lo Fclock
+
•
dIo Fclock
2 V
(
•
Vomax
• synfet
•
Vinmin Rdsonpri
)
•
+
(
Vmisc
2 D
)
–
•
–
(
11
1 D
)
–
+
2
)
• synfet
V
0
•
C), EQ. 9 produces
Io
---- -
N
) N
•
Application Note 1002
(EQ. 10)
(EQ. 11)
(EQ. 12)
(EQ. 9)
0
C)
The minimum required output capacitance (Co) can be
estimated by EQ. 13 when limiting the output ripple voltage
contributed by output capacitance to be no more than dV
In addition to meeting the requirements of ESR and Co, the
output capacitors should be able to absorb the output RMS
current, as defined in EQ. 14.
The output voltage ripple can be conservatively
approximated by EQ. 15. The first two terms (dV
dV
(ESR) and the equivalent series inductance (ESL) of the
output capacitors are the dominant ones and are normally
accurate enough to estimate the ripple voltage. The last term
(dV
normally much smaller and can be neglected since the peak
of the dV
does not align with the peak of dV
15. The positive and negative peaks of the overall ripple
voltage (sum of all three components) relative to the DC level
is not symmetric (caused by dV
converter operates at 50% duty cycle. This asymmetry
between positive and negative peaks is not a big concern in
most applications since both dV
very small compared to the ESR portion. Note that the DC
level remains constant. Refer to [6] for more details.
The ESL of a capacitor is not usually listed in databooks. It
can be practically approximated with EQ. 16:
where Fres is the resonant frequency that produces the
lowest impedance of the capacitor.
At the very edge of the transient, the equivalent ESL of all
output capacitors induces a spike, as defined in EQ. 17 for a
dV
dV
ESL
dV
Co
Voripple
Iorms
ESR
ESL
ESL
Co
Co
FIGURE 15. OUTPUT RIPPLE VOLTAGE COMPONENTS
=
=
) contributed by the output capacitance (Co) is
) contributed by the equivalent series resistance
0
0
-------------- -
dV
0
------- -
Co
=
1
1
Co
Co
≈
----------
dIo
•
12
dIo ESR
happens at the ripple current across zero and
--------------------------------- -
(
•
2π Fres
--------------------------- -
8 Fclock
•
•
•
dIo
1
+
-
+
+
)
2
ESL
----------- - Vs
Lo
+
Co
Co
------- -
Co
1
ESR
and dV
and dV
•
-
-
-
--------------------------- -
8 Fclock
, as shown in Figure
•
dIo
ESL
ESL
) unless the
are generally
ESR
(EQ. 15)
(EQ. 13)
(EQ. 14)
(EQ. 16)
and
Co
.