ISL6551EVAL1 Intersil, ISL6551EVAL1 Datasheet - Page 24

• Manufacturer Part Number: ISL6551EVAL1
• Description: EVALUATION BOARD ISL6551
• Manufacturer: Intersil

Specifications of ISL6551EVAL1

• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Isolated
• Voltage - Output: 3.3V
• Current - Output: 60A
• Voltage - Input: 36 ~ 75V
• Regulator Topology: Buck
• Frequency - Switching: 470kHz
• Board Type: Fully Populated
• Utilized Ic / Part: ISL6551
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -

Switching Waveforms
WINDING VOLTAGE AND CURRENT
Figures 24 to 29 show the voltage waveforms across the
transformer and the primary currents through it. Note that
the R22 is replaced with a 5.0” of 14AWG wire so that the
primary current can be measured at this loop, which should
be shorted when determining the ZVS load range.
The delay between the primary voltage and secondary
voltage on the leading edge, as shown in Figures 25 and 26,
is caused by the leakage inductance of the transformer. The
input voltage is applied first across the leakage inductor
resetting its current, and the voltage across the real primary
and secondary must stay zero until the current through the
leakage inductor changes in direction and reaches the value
of the reflected load. A higher load results in larger stored
energy in the leakage inductor that needs to be reset before
going into the active mode, and the longer the delay is.
There is almost no delay for zero load operation, as shown in
Figure 27.
As shown in Figure 27, with the synchronous FETs turned
on, the converter still runs at continuous mode (CCM) with a
large duty cycle even at no-load operation. Figure 28 shows
the operation waveforms with synchronous FETs off. In this
case, the synchronous FETs block any negative current,
which forces the converter to run at discontinuous mode
(DCM) cutting down the duty cycle significantly.
FIGURE 24. SYNCHRONOUS DRIVE SIGNAL. CHANNEL 1:
LOWER DRIVE SIGNAL AT ISL6551; CHANNEL 2:
SYNCHRONOUS DRIVE SIGNAL; CHANNEL 3:
LOWER DRIVE SIGNAL AT THE LOWER FET
1
24
3
Application Note 1002
2
Figure 29 shows the operation waveforms for INV_SYNC
DRIVE scheme. Since only one synchronous FET is turned
on and conducts currents during the freewheeling period, the
freewheeling current reflected to the primary is higher than
that of the INV_LOW DRIVE scheme. Hence, the INV_LOW
DRIVE scheme produces as much as 2% higher efficiency
than the INV-SYNC DRIVE scheme.
FIGURE 25. TRANSFORMER WAVEFORMS AT V
FIGURE 26. TRANSFORMER WAVEFORMS AT V
V
PRIMARY CURRENT (I
VOLTAGE (VP); CHANNEL 2: SECONDARY
VOLTAGE (VS)
V
PRIMARY CURRENT (I
VOLTAGE (VP); CHANNEL 2: SECONDARY
VOLTAGE (VS)
OUT
OUT
=3.3V, AND I
=3.3V, AND I
OUT
OUT
=60A. CHANNEL 4:
=30A. CHANNEL 4:
P)
P
); CHANNEL 3: PRIMARY
; CHANNEL 3: PRIMARY
2
3
3
2
IN
IN
=48V,
=48V,
4
4